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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

WEDPN4M72V-XB2X

January 2005

Rev. 2

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

FIGURE 4 – CAS LATENCY

If a READ command is registered at clock edge n, and

the latency is m clocks, the data will be available by clock

edge n+m. The I/Os will start driving as a result of the clock

edge one cycle earlier (n + m - 1), and provided that the

relevant access times are met, the data will be valid by

clock edge n + m. For example, assuming that the clock

cycle time is such that all relevant access times are met,

if a READ command is registered at T0 and the latency

is programmed to two clocks, the I/Os will start driving

after T1 and the data will be valid by T2. Table 2 below

indicates the operating frequencies at which each CAS

latency setting can be used.

Reserved states should not be used as unknown operation

or incompatibility with future versions may result.

OPERATING MODE

The normal operating mode is selected by setting M7and

M8 to zero; the other combinations of values for M7 and

M8 are reserved for future use and/or test modes. The

programmed burst length applies to both READ and

WRITE bursts.

A1-7 when the burst length is set to two; by A2-7 when

the burst length is set to four; and by A3-7 when the burst

length is set to eight. The remaining (least significant)

address bit(s) is (are) used to select the starting location

within the block. Full-page bursts wrap within the page if

the boundary is reached.

BURST TYPE

Accesses within a given burst may be programmed to be

either sequential or interleaved; this is referred to as the

burst type and is selected via bit M3.

The ordering of accesses within a burst is determined by

the burst length, the burst type and the starting column

address, as shown in Table 1.

CAS LATENCY

The CAS latency is the delay, in clock cycles, between

the registration of a READ command and the availability

of the first piece of output data. The latency can be set to

two or three clocks.

CK

I/O

T2

T1

T3

T0

CAS Latency = 3

LZ

t

COMMAND

NOP

READ

NOP

T4

NOP

DON’T CARE

UNDEFINED

CK

I/O

T2

T1

T3

T0

CAS Latency = 2

LZ

OH

t

COMMAND

READ

NOP

NOP