WED9LC6816V

September, 2003

Rev. 1

3

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

Contact factory for ordering information.

Output Functional Descriptions

Symbol

Type

Signal

Polarity

Function

SSCK#

Input

Pulse

Positive Edge The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock.

SSADS#

SSOE#

SSWE#

Input

Pulse

Active Low

When sampled at the positive rising edge of the clock, SSADS#, SSOE#, and SSWE# define

the operation to be executed by the SSRAM.

SSCE#

Input

Pulse

Active Low

SSCE# disable or enable SSRAM device operation.

SDCK#

Input

Pulse

Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.

SDCE

Input

Pulse

Active Low

SDRAS#

SDCAS#

SDWE#

Input

Pulse

Active Low

When sampled at the positive rising edge of the clock, SDCAS#, SDRAS#, and SDWE#

define the operation to be executed by the SDRAM.

A0-17

SDA10

Input

Level

—

Address bus for SSRAM and SDRAM

sampled at the rising clock edge.

sampled at the rising clock edge. In addition to the row address, SDA10 is used to invoke

autoprecharge is disabled.

precharge.

Input

Output

Level

—

Data Input/Output are multiplexed on the same pins.

Input

Pulse

Supply

Power and ground for the input buffers and the core logic.

,Supply

Data base power supply pins, 3.3V (2.5V future).