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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

WED9LAPC2C16V8BC

July, 2000

Rev. 0

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

SDRAM COMMAND TRUTH TABLE

NOTES:

1. All of the SDRAM operations are defined by states of VCWE#, VCRAS#, VCCAS#, and VCDQM# at the positive rising edge of the clock.

2. Bank Select (VCBS), if VCBS = 0 then bank A is selected, if VCBS = 1 then bank B is selected.

3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency.

4. The VCDQM# has two functions for the data DQ Read and Write operations. During a Read cycle, when VCDQM# goes high at a clock timing the

data outputs are disabled and become high impedance after a two clock delay. VCDQM# also provides a data mask function for Write cycles. When

it activates, the Write operation at the clock is prohibited (zero clock latency).

FUNCTION

VCRAS# VCCAS#

VCWE#

VCDQM#

VCBS

VCADDR

NOTES

Mode Register Set

L

L

L

X

OP CODE

Auto Refresh (CBR)

L

L

H

X

X

X

Precharge

Single Bank

L

H

L

X

BA

L

2

Precharge all Banks

L

H

L

X

X

H

Bank Activate

L

H

H

X

BA

Row Address

2

Write

H

L

L

X

BA

L

2

Write with Auto Precharge

H

L

L

X

BA

H

2

Read

H

L

L

X

BA

L

2

Read with Auto Precharge

H

L

H

X

BA

H

2

Burst Termination

H

H

L

X

X

X

3

No Operation

H

H

H

X

X

X

Data Write/Output Disable

X

X

X

L

X

X

4

Data Mask/Output Disable

X

X

X

H

X

X

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