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WED3EG72M18S355JD3ISG Datasheet(PDF) 7 Page - White Electronic Designs Corporation |
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WED3EG72M18S355JD3ISG Datasheet(HTML) 7 Page - White Electronic Designs Corporation |
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7 / 12 page  7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WED3EG7218S-JD3 June 2006 Rev. 2 PRELIMINARY DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS DDR400: VCC = VCCQ = +2.6V ± 0.1V; DDR333, 266, 200: VCC = VCCQ = +2.5V ± 0.2V AC Characteristics 403 335 262/265 202 Parameter Symbol Min Max Min Max Min Max Min Max Units Notes Access window of DQs from CK, CK# tAC -0.70 +0.70 -0.70 +0.70 -0.75 +0.75 -0.75 +0.75 ns CK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK 16 CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK 16 Clock cycle time CL=3 tCK (3) 5 7.5 ns 22 CL=2.5 tCK (2.5) 6 13 6 13 7.5 13 7.5 13 ns 22 CL=2 tCK (2) 7.5 13 7.5 13 7.5 13 10 13 ns 22 DQ and DM input hold time relative to DQS tDH 0.40 0.45 0.5 0.5 ns 14,17 DQ and DM input setup time relative to DQS tDS 0.40 0.45 0.5 0.5 ns 14,17 DQ and DM input pulse width (for each input) tDIPW 1.75 1.75 1.75 1.75 ns 17 Access window of DQS from CK, CK# tDQSCK -0.60 +0.60 -0.60 +0.60 -0.75 +0.75 -0.75 +0.75 ns DQS input high pulse width tDQSH 0.35 0.35 0.35 0.35 tCK DQS input low pulse width tDQSL 0.35 0.35 0.35 0.35 tCK DQS-DQ skew, DQS to last DQ valid, per group, per access tDQSQ 0.40 0.45 0.5 0.5 ns 13,14 Write command to first DQS latching transition tDQSS 0.72 1.28 0.75 1.25 0.75 1.25 0.75 1.25 tCK DQS falling edge to CK rising - setup time tDSS 0.2 0.2 0.2 0.2 tCK DQS falling edge from CK rising - hold time tDSH 0.2 0.2 0.2 0.2 tCK Half clock period tHP tCH, tCL tCH, tCL tCH, tCL tCH, tCL ns 18 Data-out high-impedance window from CK, CK# tHZ +0.70 +0.70 +0.75 +0.75 ns 8,19 Data-out low-impedance window from CK, CK# tLZ -0.70 -0.70 -0.75 -0.75 ns 8,20 Address and control input hold time (fast slew rate) tIHf 0.60 0.75 0.90 0.90 ns 6 Address and control input set-up time (fast slew rate) tISf 0.60 0.75 0.90 0.90 ns 6 Address and control input hold time (slow slew rate) tIHs 0.60 0.80 1 1 ns 6 Address and control input setup time (slow slew rate) tISs 0.60 0.80 1 1 ns 6 Address and control input pulse width (for each input) tIPW 2.2 2.2 2.2 2.2 ns LOAD MODE REGISTER command cycle time tMRD 10 12 15 15 ns DQ-DQS hold, DQS to first DQ to go non-valid, per access tQH tHP-tQHS tHP-tQHS tHP-tQHS tHP-tQHS ns 13,14 Data hold skew factor tQHS 0.50 0.55 0.75 0.75 ns ACTIVE to PRECHARGE command tRAS 40 70,000 42 70,000 40 120,000 45 120,000 ns 15 ACTIVE to READ with Auto precharge command tRAP 15 15 15 20 ns ACTIVE to ACTIVE/AUTO REFRESH command period tRC 55 60 60 65 ns AUTO REFRESH command period tRFC 70 72 75 75 ns 21 |
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