WE512K8, WE256K8,

WE128K8-XCX

9

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

May 2000

Rev. 1

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

PAGE MODE CHARACTERISTICS

Parameter

Symbol

Min

Max

Unit

Write Cycle Time, TYP = 6mS

10

ms

Data Set-up Time

100

ns

Data Hold Time

10

ns

Write Pulse Width

150

ns

Byte Load Cycle Time

150

µs

Write Pulse Width High

50

ns

Device

Block Address

Page Address

WE512K8-XCX

A17-A18

A7-A16

WE256K8-XCX

A15-A17

A6-A14

WE128K8-XCX

A15-A16

A6-A14

PAGE WRITE OPERATION

These devices have a page write operation that allows one

to 64 bytes of data (one to 128 bytes for the WE512K8) to

be written into the device and then simultaneously written

during the internal programming period. Successive bytes

may be loaded in the same manner after the first data

byte has been loaded. An internal timer begins a time

out operation at each write cycle. If another write cycle

is completed within 150µs or less, a new time out period

begins. Each write cycle restarts the delay period. The write

cycles can be continued as long as the interval is less than

the time out period.

The usual procedure is to increment the least significant

WE512K8) at each write cycle. In this manner a page of

up to 64 bytes (128 bytes for the WE512K8) can be loaded

into the EEPROM in a burst mode before beginning the

relatively long interval programming cycle.

After the 150µs time out is completed, the EEPROM

begins an internal write cycle. During this cycle the entire

page of bytes will be written at the same time. The internal

programming cycle is the same regardless of the number

of bytes accessed.

FIGURE 9 – PAGE WRITE WAVEFORMS

NOTE:

1. Decoded Address Lines must be valid for the duration of the write.

OE#

ADDRESS (1)

CS#

WE#

DATA

The page address must be the same for each byte load

and must be valid during each high to low transition of

WE# (or CS#). The block address also must be the same

for each byte load and must remain valid throughout the

WE# (or CS#) low pulse. The page and block address

lines are summarized below: