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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

WED3DL328V

June, 2002

Rev. 1

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

Function

CKE

CE# RAS# CAS# WE# DQM

BA A10/AP

A9-0

A11

Notes

Previous

Cycle

Current

Cycle

Register

Mode Register Set

H

X

L

L

L

L

X

OP CODE

Refresh

Auto Refresh (CBR)

H

H

L

L

L

H

X

X

X

X

Entry Self Refresh

H

L

L

L

L

H

X

X

X

X

Precharge

Single Bank Precharge

H

X

L

L

H

L

X

BA

L

X

2

Precharge all Banks

H

X

L

L

H

L

X

X

H

X

Bank Activate

H

X

L

L

H

H

X

BA

Row Address

2

Write

H

X

L

H

L

L

X

BA

L

Column

2

Write with Auto Precharge

H

X

L

H

L

L

X

BA

H

Column

2

Read

H

X

L

H

L

L

X

BA

L

Column

2

Read with Auto Precharge

H

X

L

H

L

H

X

BA

H

Column

2

Burst Termination

H

X

L

H

H

L

X

X

X

X

3

No Operation

H

X

L

H

H

H

X

X

X

X

Device Deselect

H

X

H

X

X

X

X

X

X

X

Clock Suspend/Standby Mode

L

X

X

X

X

X

X

X

X

X

4

Data Write/Output Disable

H

X

X

X

X

X

L

X

X

X

5

Data Mask/Output Disable

H

X

X

X

X

X

H

X

X

X

5

Power Down Mode

Entry

X

L

H

X

X

X

X

X

X

X

6

Exit

X

H

H

X

X

X

X

X

X

X

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COMMAND TRUTH TABLE

Notes:

1. All of the SDRAM operations are defined by states of CE#, WE#, RAS#, CAS#, and DQM at the positive rising edge of the clock.

2. Bank Select (BA), if BA = 0 then bank A is selected, if BA = 1 then bank B is selected.

3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS# latency.

4. During normal access mode, CKE is held high and CK is enabled. When it is low, it freezes the internal clock and extends data Read and Write operations. One

clock delay is required for mode entry and exit.

5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the data outputs are disabled

and become high impedance after a two clock delay. DQM also provides a data mask function for Write cycles. When it activates, the Write operation at the

clock is prohibited (zero clock latency).

All banks must be precharged before entering the Power Down Mode. The Power Down Mode does not preform any Refresh operations, therefore the device can’t