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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

WED3C7558M-XBX

August 2002

Rev. 7

POWER CONSUMPTION

Processor (CPU) Frequency/L2 Frequency

Unit

Notes

300/150 MHz

350/175MHz

Full-on Mode

Typical

4.1

4.6

W

1, 3

Maximum

6.7

7.9

W

1, 2

Doze Mode

Maximum

2.5

2.8

W

1, 2

Nap Mode

Maximum

1700

1800

mW

1, 2

Sleep Mode

Maximum

1200

1300

mW

1, 2

Sleep Mode–PLL and DLL Disabled

Maximum

500

500

mW

1, 2

NOTES:

1.

2.

3.

L2 CACHE CONTROL REGISTER (L2CR)

The L2 cache control register, shown in Figure 5, is a supervisor-level, implementation-specific SPR used to configure

and operate the L2 cache. It is cleared by hard reset or power-on reset.

The L2CR bits are described in Table 1.

FIGURE 5 – L2 CACHE CONTROL REGISTER (L2CR)

L2E

L2SIZ

L2CLK

L2RAM

L2I

L20H

0

0

L2CTR

0

1

2

3

4

6

7

8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

30

31

L2PE

L2DO

L2CTL

L2TS

L2SL

L2BYP

L2IO

L2DRO

L2IP

L2WT

L2DF

L2CS

Reserved