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WED3C7410E16M-XBX Datasheet(PDF) 8 Page - White Electronic Designs Corporation

Part # WED3C7410E16M-XBX
Description  RISC Microprocessor Multichip Package
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Manufacturer  WEDC [White Electronic Designs Corporation]
Direct Link  http://www.whiteedc.com
Logo WEDC - White Electronic Designs Corporation

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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WED3C7410E16M-XBX
May 2006
Rev. 9
L2 CACHE CONTROL REGISTER (L2CR)
The L2 cache control register, shown in Figure 5, is a supervisor-level, implementation-specific SPR used to configure
and operate the L2 cache. It is cleared by hard reset or power-on reset.
BGA THERMAL RESISTANCE
Description
Symbol
PPC
SSRAM
Units
Notes
Junction to Ambient (No Airflow)
Theta JA
14.0
10.3
C/W
1
Junction to Ball
Theta JB
8.9
5.2
C/W
1
Junction to Case (Top)
Theta JC
0.1
0.1
C/W
1
NOTE 1: Refer to PBGA Thermal Resistance Correlation at www.whiteedc.com in the application notes section for modeling conditions
POWER CONSUMPTION
VCC = AVCC = 1.8 ±0.1V VDC, L2VCC = 3.3V ±5% VDC, GND = 0 VDC, 0
≤ TJ < 105°C
Processor (CPU) Frequency/L2 Frequency
Unit
Notes
400MHz/200MHz
450MHz/200MHz
Full-on Mode
Typical
5.7
6.2
W
1, 3
Maximum
13.1
14.3
W
1, 2
Doze Mode
Maximum
5.3
5.8
W
1, 2
Nap Mode
Maximum
2.25
2.4
W
1, 2
Sleep Mode
Maximum
2.20
2.35
W
1, 2
Sleep Mode–PLL and DLL Disabled
Maximum
2.0
2.0
W
1, 2
NOTES:
1.
These values apply for all valid system bus and L2 bus ratios. The values do not include OVCC; AVCC and L2AVCC suppling power. OVCC power is system dependent, but is typically
<10% of VCC power. Worst case power consumption, for AVCC = 15mW and L2AVCC = 15mW.
2.
Maximum power is measured at VCC = 1.9 V while running an entirely cache-resident, contrived sequence of instructions which keep the execution units maximally busy.
3.
Typical power is an average value measured at VCC = AVCC = L2AVCC = 1.8V, OVCCd = L2OVCC = 2.5V in a system, executing typical applications and benchmark sequences.
4.
At a maximum 60x bus frequency of 133MHz, the maximum configurtable core frequency is 400MHz.
FIGURE 5 – L2 CACHE CONTROL REGISTER (L2CR)
The L2CR bits are described in Table 1.
L2E
L2SIZ
L2CLK
L2RAM
L21
L2OH
0000000
0
1
2
3
4
6
7
8
9
10 11 12 13 14
15 16 17 18 19 20 21 22 22 24
30 31
L2IP
L2PE
L2DO
L2CTL
L2TS
L2SL
L2BYP L2HWF L2IO L2DRO
L2WT
L2DF
L2FA
L2CLKSTP


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