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WE32K32N-150G2UM Datasheet(PDF) 6 Page - White Electronic Designs Corporation |
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WE32K32N-150G2UM Datasheet(HTML) 6 Page - White Electronic Designs Corporation |
6 / 13 page 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs WE32K32-XXX March 2006 Rev. 4 White Electronic Designs Corp. reserves the right to change products or specifications without notice. AC Read Characteristics (See Figure 6) VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C READ CYCLE Symbol -80 -90 -120 -150 Unit Parameter Min Max Min Max Min Max Min Max Read Cycle Time tRC 80 90 120 150 ns Address Access Time tACC 80 90 120 150 ns CS Access Time tACS 80 90 120 150 ns Output Hold from Add. Change, OE# or CS# tOH 0000 ns Output Enable to Output Valid tOE 40 50 85 85 ns Chip Select or OE# to Output in High Z tDF 40 50 70 70 ns READ The WE32K32-XXX stores data at the memory location determined by the address pins. When CS# and OE# are low and WE# is high, this data is present on the outputs. When CS# and OE# are high, the outputs are in a high impedance state. This 2 line control prevents bus contention. FIGURE 6 – READ WAVEFORMS NOTES: 1. OE# may be delayed up to tACS - tOE after the falling edge of CS# without impact on tOE or by tACC - tOE after an address change without impact on tACC. 2. tCHZ, tOHZ are specified from OE# or CS# whichever occurs first (CL = 5pF). 3. All I/O transitions are measured ±200 mV from steady state with loading as specified in "Load Test Circuits." t ADDRESS CS# OE# OUTPUT OH tDF t ACC t RC t OE tACS OUTPUT VALID ADDRESS VALID HIGH Z |
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