 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
W332M72V-125SBC Datasheet(PDF) 1 Page - White Electronic Designs Corporation |
|
||||||||||||||||||||||||||||||
W332M72V-125SBC Datasheet(HTML) 1 Page - White Electronic Designs Corporation |
|
|
1 / 15 page  1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W332M72V-XSBX Ju;y 2006 Rev. 3 GENERAL DESCRIPTION The 256MByte (2Gb) SDRAM is a high-speed CMOS, dynamic random-access, memory using 5 chips containing 536,870,912 bits. Each chip is internally configured as a quad-bank DRAM with a synchronous interface. Each of the chip’s 134,217,728-bit banks is organized as 8,192 rows by 1,024 columns by 16 bits. Read and write accesses to the SDRAM are burst ori- ented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0- 12 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option. An AUTO PRECHARGE function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The 2Gb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high- speed, random-access operation. The 2Gb SDRAM is designed to operate at 3.3V. An auto refresh mode is provided, along with a power-saving, power-down mode. 32Mx72 Synchronous DRAM FEATURES High Frequency = 100, 125, 133MHz Package: • 208 Plastic Ball Grid Array (PBGA), 16 x 22mm 3.3V ±0.3V power supply for core and I/Os Fully Synchronous; all signals registered on positive edge of system clock cycle Internal pipelined operation; column address can be changed every clock cycle Internal banks for hiding row access/precharge Programmable Burst length 1,2,4,8 or full page 8192 refresh cycles Commercial, Industrial and Military Temperature Ranges Organized as 32M x 72 Weight: W332M72V-XSBX - 2.0 grams typical BENEFITS 73% SPACE SAVINGS Reduced part count Reduced I/O count • 23% I/O Reduction Reduced trace lengths for lower parasitic capacitance Suitable for hi-reliability applications Laminate interposer for optimum TCE match * This product is subject to change without notice. Discrete Approach ACTUAL SIZE S A V I N G S Area 5 x 265mm2 = 1325mm2 352mm2 73% I/O 5 x 54 pins = 270 pins 208 Balls 23% Count 16 22 11.9 11.9 11.9 11.9 11.9 22.3 54 TSOP 54 TSOP 54 TSOP 54 TSOP 54 TSOP White Electronic Designs W332M72V-XSBX |
Similar Part No. - W332M72V-125SBC |
|
Similar Description - W332M72V-125SBC |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
