W3H64M72E-XSBX

11

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

March 2006

Rev. 1

ADVANCED*

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

CAS LATENCY (CL)

The CAS latency (CL) is defined by bits M4–M6, as shown

in Figure 5. CL is the delay, in clock cycles, between the

registration of a READ command and the availability of

the first bit of output data. The CL can be set to 3, 4, 5,

or 6 clocks, depending on the speed grade option being

used.

DDR2 SDRAM does not support any half-clock latencies.

Reserved states should not be used as unknown operation

or incompatibility with future versions may result.

DDR2 SDRAM also supports a feature called posted

CAS additive latency (AL). This feature allows the READ

internal command to the DDR2 SDRAM by AL clocks.

Examples of CL = 3 and CL = 4 are shown in Figure 6;

both assume AL = 0. If a READ command is registered

at clock edge n, and the CL is m clocks, the data will be

available nominally coincident with clock edge n+m (this

assumes AL = 0).

n + 3

n + 2

n + 1

CK

CK#

COMMAND

DQ

DQS, DQS#

CL = 3 (AL = 0)

READ

Burst length = 4

Posted CAS# additive latency (AL) = 0

Shown with nominal

t AC, tDQSCK, and tDQSQ

T0

T1

T2

DON’T CARE

TRANSITIONING DATA

NOP

NOP

NOP

n

T3

T4

T5

NOP

NOP

T6

NOP

n + 3

n + 2

n + 1

CK

CK#

COMMAND

DQ

DQS, DQS#

CL = 4 (AL = 0)

READ

T0

T1

T2

NOP

NOP

NOP

n

T3

T4

T5

NOP

NOP

T6

NOP

FIGURE 6 – CAS LATENCY (CL)