W3H64M72E-XSBX

8

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

March 2006

Rev. 1

ADVANCED*

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

NOTES:

1.

be applied to the ODT ball (all other inputs may be undefined, I/Os and outputs

latch-up). At least one of the following two sets of conditions (A or B) must be

Conditions table):

Operating Conditions table specifications apply.

supply ramp time.

ramping, for both AC and DC levels, until supply voltage ramping completes

Operating Conditions table specifications apply.

2.

CKE uses LVCMOS input levels prior to state T0 to ensure DQs are High-Z during

SSTL_18 input levels. Once CKE transitions to a high level, it must stay HIGH for

the duration on the initialization sequence.

3.

PRE = PRECHARGE command, LM = LOAD MODE command, MR = Mode

Register, EMR = extended mode register, EMR2 = extended mode register 2,

EMR3 = extended mode register 3, REF = REFRESH command, ACT = ACTIVE

command, A10 = PRECHARGE ALL, CODE = desired value for mode registers

(blank addresses are required to be decoded), VALID - any valid command/

address, RA = row address, bank address.

4.

DM represents UDM & LDM, DQS represents, UDQS, UDQS#, LDQS, LDQS#,

RDQS, RDQS#, DQ represents DQ0-71.

5.

For a minimum of 200µs after stable power and clock (CK, CK#), apply NOP or

DESELECT commands, then take CKE HIGH.

6.

Wait a minimum of 400ns, then issue a PRECHARGE ALL command.

7.

Issue a LOAD MODE command to the EMR(2). (To issue an EMR(3) command,

provide LOW to BA2 and BA0, and provide HIGH to BA1.) Set register E7 to "0" or

"1;" all others must be "0".

8.

Issue LOAD MODE command to the EMR(3). (to issue and EMR(3) command,

provide HIGH to BA0 = 1, BA1 = 1, and BA2 = 0.) Set all registers to "0".

9.

Issue a LOAD MODE command to the EMR to enable DLL. To issue a CLL

ENABLE command provide LOW to BA1, BA2 and A0; provide HIGH to BA0. Bits

E7, E8 and E9 can be set to "0" or "1;" Micron recommends setting them to "0".

10. Issue a LOAD MODE command for DLL RESET. 200 cycles of clock input is

required to lock the DLL. (To issue a DLL RESET, provide HIGH to A8 and provide

LOW to BA2 = BA1 = BA0 = 0.) CKE must be HIGH the entire time. .

11. Issue PRECHARGE ALL command.

12. Issue two or more REFRESH commands.

13. Issue a LOAD MODE command with LOW to A8 to initialize device operation (i.e.,

to program operating parameters without resetting the DLL). To access the mode

registers, BA0 = 0, BA1 = 0, BA2 = 0.

14. Issue a LOAD MODE command to the EMR to enable OCD default by setting bits

E7, E8, and E9 to “1,” and then setting all other desired parameters. To access the

extended mode register, BA2 = 0, BA1 = 0, BA0 = 1.

15. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7,

E8, and E9 to “0,” and then setting all other desired parameters. To access the

extended mode registers, BA2 = 0, BA1 = 0, BA0 = 1.

16. The DDR2 SDRAM is now initialized and ready for normal operation 200 clock

cycles after the DLL RESET at Tf0.