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W3EG72126MS166AJD3MF Datasheet(PDF) 6 Page - White Electronic Designs Corporation

Part # W3EG72126MS166AJD3MF
Description  1GB-128Mx72 DDR SDRAM REGISTERED ECC w/PLL
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Manufacturer  WEDC [White Electronic Designs Corporation]
Direct Link  http://www.whiteedc.com
Logo WEDC - White Electronic Designs Corporation

W3EG72126MS166AJD3MF Datasheet(HTML) 6 Page - White Electronic Designs Corporation

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White Electronic Designs
W3EG72126S-D3
-JD3
-AJD3
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
November 2004
Rev. 3
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C
≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V
Includes PLL and register power
Parameter
Symbol
Conditions
DDR333@CL=2.5
Max
DDR266@CL=2, 2.5
Max
DDR200@CL=2
Max
Units
Operating Current
IDD0
One device bank; Active - Precharge;
tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control
inputs changing once every two
cycles.
2615
2615
2615
mA
Operating Current
IDD1
One device bank; Active-Read-
Precharge Burst = 2; tRC=tRC (MIN);
tCK=tCK (MIN); lOUT = 0mA; Address
and control inputs changing once per
clock cycle.
3155
3155
3155
mA
Precharge Power-
Down Standby
Current
IDD2P
All device banks idle; Power-down
mode; tCK=tCK (MIN); CKE=(low)
90
90
90
rnA
Idle Standby Current
IDD2F
CS# = High; All device banks idle;
tCK=tCK (MIN); CKE = high; Address
and other control inputs changing
once per clock cycle. VIN = VREF for
DQ, DQS and DM.
1120
1120
1120
mA
Active Power-Down
Standby Current
IDD3P
One device bank active; Power-Down
mode; tCK (MIN); CKE=(low)
630
630
630
mA
Active Standby
Current
IDD3N
CS# = High; CKE = High; One device
bank; Active-Precharge; tRC=tRAS
(MAX); tCK=tCK (MIN); DQ, DM and
DQS inputs changing twice per clock
cycle; Address and other control
inputs changing once per clock cycle.
1210
1210
1210
mA
Operating Current
IDD4R
Burst = 2; Reads; Continuous burst;
One device bank active; Address
and control inputs changing once
per clock cycle; TCK= TCK (MIN); lOUT
= 0mA.
3245
3245
3245
mA
Operating Current
IDD4W
Burst = 2; Writes; Continuous burst;
One device bank active; Address
and control inputs changing once per
clock cycle; tCK=tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle.
3425
3065
3065
rnA
Auto Refresh
Current
IDD5
tRC = tRC (MIN)
5530
5530
5530
mA
Self Refresh Current
IDD6
CKE
≤ 0.2V
400
400
400
mA
Operating Current
IDD7A
Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC
(MIN); tCK=tCK (MIN); Address and
control inputs change only during
Active Read or Write commands.
7565
7475
7475
mA


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