W3H64M72E-XSBX

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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

March 2006

Rev. 1

ADVANCED*

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

TABLE 1 – BALL DESCRIPTIONS

Symbol

Type

Description

ODT

Input

On-Die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM. When

enabled, ODT is only applied to each of the following balls: DQ0–DQ71, LDM, UDM, LDQS, LDQS#, UDQS, and

UDQS#. The ODT input will be ignored if disabled via the LOAD MODE command.

CK, CK#

Input

Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing

of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS/DQS#) is referenced to the

crossings of CK and CK#.

CKE

Input

Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates clocking circuitry on the

DDR2 SDRAM. The specific circuitry that is enabled/disabled is dependent on the DDR2 SDRAM configuration

and operating mode. CKE LOW provides PRECHARGE power-down mode and SELF-REFRESH action (all banks

idle), or ACTIVE power-down (row active in any bank). CKE is synchronous for power-down entry, Power-down

exit, output disable, and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (excluding

CKE, and ODT) are disabled during power-down. Input buffers (excluding CKE) are disabled during self refresh.

CS#

Input

Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands

are masked when CS# is registered HIGH.

RAS#, CAS#,

WE#

Input

Command inputs: RAS#, CAS#, WE# (along with CS#) define the command being entered.

LDM, UDM

Input

Input data mask: DM is an input mask signal for write data. Input data is masked when DM is concurrently sampled

HIGH during a WRITE access. DM is sampled on both edges of DQS. Although DM balls are input-only, the DM

loading is designed to match that of DQ and DQS balls. LDM is DM for lower byte DQ0–DQ7 and UDM is DM for

upper byte DQ8–DQ15, of each of U0-U4

BA0–BA2

Input

Bank address inputs: BA0–BA2 define to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is

being applied. BA0–BA2 define which mode register including MR, EMR, EMR(2), and EMR(3) is loaded during the

LOAD MODE command.

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