W3HG264M72EER665AD7XG datasheet(6/14 Pages) WEDC

Part #	W3HG264M72EER665AD7XG

Description	1GB - 2x64Mx72 DDR2 SDRAM REGISTERED, w/PLL, VLP Mini-DIMM

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Manufacturer	WEDC [White Electronic Designs Corporation]

Direct Link	http://www.whiteedc.com

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6 / 14 page

W3HG264M72EER-AD7

December 2005

Rev. 0

ADVANCED

6

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

DDR2 ICC SPECIFICATIONS AND CONDITIONS

Includes DDR2 SDRAM components only; TA = 0°C, VCC = 1.9V

Symbol Parameter

Condition

806

667

534

403

Unit

ICCO*

Operating one bank

active-precharge;

tCK = tCK(I

CC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is

HIGH between valid commands; Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

TBD

1,525

1,615

1,795

mA

ICC1*

Operating one

bank active-read-

precharge;

IOUT = OmA; BL = 4; CL = CL(ICC); tCK = tCK(I

CC); tRC = tRC(ICC); tRAS = tRAS

MIN(ICC); CKE is HIGH, CS# is HIGH between valid commands; Address

bus inputs are SWITCHING; Data bus inputs are SWITCHING; Data

pattern is sames as ICC4W.

TBD

1,615

1,750

1,930

mA

ICC2P**

Precharge power-

down current;

All banks idle; tCK = tCK(I

CC); CKE is LOW; Other control and address

bus inputs are STABLE; Data bus inputs are FLOATING

TBD

490

mA

ICC2Q**

Precharge quite

standby current;

All banks idle; tCK = tCK(I

CC); CKE is HIGH; CS# is HIGH; Other control

and address bus inputs are STABLE; Data bus inputs are FLOATING

TBD

1,030

1,120

1,300

mA

ICC2N**

Precharge standby

current;

All banks idle; tCK = tCK(I

CC); CKE is HIGH; CS# is HIGH; Other control

and address bus inputs are STABLE; Data bus inputs are SWITCHING

TBD

1,120

1,210

1,390

mA

ICC3P**

Active power-down

current;

All banks open; tCK = tCK(I

CC), CKE is LOW;

Other control and address bus inputs are

STABLE; Data bus inputs are FLOATING

Fast PDN Exit

MRS(12) = 0

TBD

1,030

1,165

1,300

mA

Slow PDN Exit

MRS(12) = 1

TBD

895

985

1,075

mA

ICC3N**

Active standby

current;

All banks open; tCK = tCK(I

CC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE

is HIGH, CS# is HIGH between valid commands; Other control and

address bus inputs are SWITCHING; Data bus inputs are SWITCHING

TBD

1,210

1,390

1,570

mA

ICC4W*

Operating burst

write current;

All banks open; Continuous burst writes; BL = 4; CL = CL(ICC); AL =

0; tCK = tCK(I

CC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is HIGH, CS# is

HIGH between valid commands; Address bus inputs are SWITCHING;

Data bus inputs are SWITCHING

TBD

1,840

2,155

2,470

mA

ICC4R*

Operating burst

read current;

All banks open; Continuous burst reads; TOUT = OmA; BL = 4; CL =

CL(ICC); AL = 0; tCK = tCK(I

CC); tRC = tRC(ICC); tRAS = tRAS MIN(ICC); CKE is

HIGH, CS# is HIGH between valid commands; Address bus inputs are

SWITCHING; Data pattern is same as ICC4W.

TBD

1,840

2,200

2,560

mA

ICC5**

Burst auto refresh

current;

tCK = tCK(I

CC); Refresh command at every tRC(ICC) interval; CKE is HIGH;

CS# is HIGH between valid commands; Other control and address bus

inputs are SWITCHING; Data bus inputs are SWITCHING

TBD

2,515

2,695

2,875

mA

ICC6**

Self refresh current;

CK and CK# at OV; CKE < 0.2V; Other control

and address bus inputs are FLOATING; Data

bus inputs are FLOATING

Normal

TBD

90

mA

ICC7*

Operating bank

interleave read

curent;

All bank interleaving reads; IOUT = OmA; BL = 4; CL = CL(ICC); AL

= tRCD(I

CC) - 1*tCK(ICC); tCK = tCK(ICC); tRC = tRC(ICC); tRRD = tRRD MIN(ICC)

= 1*tCK(I

CC); CKE is HIGH; CS# is HIGH between valid commands;

Address bus inputs are STABLE during DESELECTs; Data bus inputs

are SWITCHING

TBD

2,875

3,235

3,415

mA

Notes:

ICC speciﬁcation is based on MICRON components. Other DRAM manufacturers speciﬁcation may be different.

* Value calculated as one module rank in this operating condition, and all other module ranks in ICC2P ( CKE LOW) mode.

** Value calculated reﬂects all module ranks in this operating condition.

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