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W3EG72125S-AJD3 Datasheet(PDF) 9 Page - White Electronic Designs Corporation |
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W3EG72125S-AJD3 Datasheet(HTML) 9 Page - White Electronic Designs Corporation |
9 / 14 page W3EG72125S-D3 -JD3 -AJD3 November 2004 Rev. 2 PRELIMINARY 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs White Electronic Designs Corp. reserves the right to change products or specifications without notice. DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (continued) 0°C ≤ TA ≤ +70°C; VCC = +2.5V ±0.2V, VCCQ = +2.5V ±0.2V AC Characteristics 335 262/263/265 202 Parameter Symbol Min Max Min Max Min Max Units Notes ACTIVE to READ or WRITE delay tRCD 18 20 20 ns PRECHARGE command period tRP 18 20 20 ns DQS read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK 19 DQS read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK ACTIVE bank a to ACTIVE bank b command tRRD 12 15 15 ns DQS write preamble tWPRE 0.25 0.25 0.25 tCK DQS write preamble setup time tWPRES 0 0 0 ns 10,11 DQS write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK 9 Write recovery time tWR 15 15 15 ns Internal WRITE to READ command delay tWTR 111 tCK Data valid output window NA tQH-tDQSQ tQH-tDQSQ tQH-tDQSQ ns 13 REFRESH to REFRESH command interval tREFC 70.3 70.3 70.3 μs 12 Average periodic refresh interval tREFI 7.8 7.8 7.8 μs 12 Terminating voltage delay to VCC tVTD 000 ns Exit SELF REFRESH to non-READ command tXSNR 75 75 80 ns Exit SELF REFRESH to READ command tXSRD 200 200 200 tCK |
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