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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

W3EG72128S-AD4

-BD4

August 2005

Rev. 3

PRELIMINARY

32. Normal Output Drive Curves:

a. The full variation in driver pull-down current from minimum to maximum process,

temperature and voltage will lie within the outer bounding lines of the V-I curve

of Figure 8, Pull-Down Characteristics.

b. The variation in driver pull-down current within nominal limits of voltage and

temperature is expected, but not guaranteed, to lie within the inner bounding

lines of the V-I curve of Figure 8, Pull-Down Characteristics.

c. The full variation in driver pull-up current from minimum to maximum process,

temperature and voltage will lie within the outer bounding lines of the V-I curve

of Figure 9, Pull-Up Characteristics.

d. The variation in driver pull-up current within nominal limits of voltage and

temperature is expected, but not guaranteed, to lie within the inner bounding

lines of the V-I curve of Figure 9, Pull-Up Characteristics.

e. The full variation in the ratio of the maximum to minimum pull-up and pull-down

current should be between 0.71 and 1.4, for device drain-to-source voltages

from 0.1V to 1.0V, and at the same voltage and temperature.

f. The full variation in the ratio of the nominal pull-up to pull-down current should

be unity ±10 percent, for device drain-to-source volt-ages from 0.1V to 1.0V.

test load. In practice, the voltage levels obtained from a properly terminated bus will

provide significantly different voltage values.

-1.5V for a pulse width !5 3ns and the pulse width can not be greater than 1/3 of the

cycle rate.

supply and the input pin.

39. The current part operates below the slowest JEDEC operating frequency of 83

MHz. As such, future die may not reflect this option.

40. Random addressing changing and 50 percent of data changing at every transfer.

41. Random addressing changing and 100 percent of data changing at every transfer.

42. CKE must be active (high) during the entire time a refresh command is executed.

That is, from the time the AUTO REFRESH command is registered, CKE must be

active at each rising clock edge, until tREF later.

44. Whenever the operating frequency is altered, not including jitter, the DLL is required

to be reset. This is followed by 200 clock cycles.

45. Leakage number reflects the worst case leakage possible through the module pin,

not what each memory device contributes.

46. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or

LOW.

120,000ns at any slower frequency.