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W3EG72128S265BD4-XG Datasheet(PDF) 8 Page - White Electronic Designs Corporation |
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W3EG72128S265BD4-XG Datasheet(HTML) 8 Page - White Electronic Designs Corporation |
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8 / 14 page  8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG72128S-AD4 -BD4 August 2005 Rev. 3 PRELIMINARY DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued) AC CHARACTERISTICS 335 262 265/202 PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES Address and control input setup time (slow slew rate) tISS 0.8 1 1 ns 12 Address and Control input pulse width (for each input) tIPW 2.2 2.2 2.2 ns LOAD MODE REGISTER command cycle time tMRD 12 15 15 ns DQ-DQS hold, DQS to first DQ to go non-valid, per access tQH tHP - tQHS tHP - tQHS tHP - tQHS ns 22, 23 Data hold skew factor tQHS 0.50 0.75 0.75 ns ACTIVE to PRECHARGE command tRAS 42 70,000 40 120,000 40 120,000 ns 30, 47 ACTIVE to READ with Auto precharge command tRAP 15 15 20 ns ACTIVE to ACTIVE/AUTO REFRESH command period tRC 60 60 65 ns AUTO REFRESH command period tRFC 72 75 78 ns 42 ACTIVE to READ or WRITE delay tRCD 15 15 20 ns PRECHARGE command period tRP 15 15 20 ns DQS read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK 37 DQS read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK 37 ACTIVE bank a to ACTIVE bank b command tRRD 12 15 15 ns DQS write preamble tWPRE 0.25 0.25 0.25 tCK DQS write preamble setup time tWPRES 0 0 0 ns 18, 19 DQS write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK 17 Write recovery time tWR 15 15 15 ns Internal WRITE to READ command delay tWTR 111 tCK Data valid output window NA tQH -tDQSQ tQH -tDQSQ tQH - tDQSQ ns 22 REFRESH to REFRESH command interval tREFC 70.3 70.3 70.3 µs 21 Average periodic refresh interval tREFI 7.8 7.8 7.8 µs 21 Terminating voltage delay to VCC tVTD 000 ns Exit SELF REFRESH to non-READ command tXSNR 75 75 75 ns Exit SELF REFRESH to READ command tXSRD 200 200 200 tCK |
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