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W3EG72128S-AD4 Datasheet(PDF) 1 Page - White Electronic Designs Corporation |
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W3EG72128S-AD4 Datasheet(HTML) 1 Page - White Electronic Designs Corporation |
1 / 14 page 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG72128S-AD4 -BD4 August 2005 Rev. 3 PRELIMINARY* OPERATING FREQUENCIES DDR333 @CL=2.5 DDR266 @CL=2 DDR266 @CL=2.5 DDR200 @CL=2 Clock Speed 166MHz 133MHz 133MHz 100MHz CL-tRCD-tRP 2.5-3-3 2-2-2 2.5-3-3 2-2-2 1GB – 2x64Mx72 DDR SDRAM UNBUFFERED ECC w/PLL FEATURES Double-data-rate architecture DDR200, DDR266 and DDR333 Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Dual Rank Power supply: 2.5V ± 0.20V JEDEC standard 200 pin SO-DIMM package • Package height options: AD4: 35.5 mm (1.38") and BD4: 31.75 mm (1.25") NOTE: Consult factory for availability of: • RoHS compliant products • Vendor source control options • Industrial temperature option DESCRIPTION The W3EG72128S is a 2x64Mx72 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM components. This module consists of eighteen 64Mx8 bit DDR SDRAMs in 66 pin TSOP packages mounted on a 200 pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * This product is under development, is not qualified or characterized and is subject to change without notice. |
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