W3EG7266S-AD4

-BD4

10

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

October 2004

Rev. 7

PRELIMINARY

test load. In practice, the voltage levels obtained from a properly terminated bus will

provide significantly different voltage values.

pulse width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate.

supply and the input pin.

39. The current part operates below the slowest JEDEC operating frequency of 83

MHz. As such, future die may not reflect this option.

40. Random addressing changing and 50 percent of data changing at every transfer.

41. Random addressing changing and 100 percent of data changing at every transfer.

42. CKE must be active (high) during the entire time a refresh command is executed.

That is, from the time the AUTO REFRESH command is registered, CKE must be

44. Whenever the operating frequency is altered, not including jitter, the DLL is required

to be reset. This is followed by 200 clock cycles (before READ commands).

45. Leakage number reflects the worst case leakage possible through the module pin,

not what each memory device contributes.

46. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or

LOW.

120,000ns at any slower frequency.