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W3EG6433S-BD4 Datasheet(PDF) 7 Page - White Electronic Designs Corporation |
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W3EG6433S-BD4 Datasheet(HTML) 7 Page - White Electronic Designs Corporation |
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7 / 13 page  7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG6433S-AD4 -BD4 May 2005 Rev. 1 PRELIMINARY White Electronic Designs Corp. reserves the right to change products or specifications without notice. DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS AC CHARACTERISTICS 335 262 265/202 UNITS NOTES PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX Access window of DQs from CK/CK# tAC -0.70 +0.70 -0.75 +0.75 -0.75 +0.75 ns CK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK 26 CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK 26 Clock cycle time CL = 2.5 tCK (2.5) 6 13 7.5 13 7.5 13 ns 40, 45 CL = 2 tCK (2) 7.5 13 7.5 13 7.5/10 13 ns 40, 45 DQ and DM input hold time relative to DQS tDH 0.45 0.5 0.5 ns 23, 27 DQ and DM input setup time relative to DQS tDS 0.45 0.5 0.5 ns 23, 27 DQ and DM input pulse width (for each input) tDIPW 1.75 1.75 1.75 ns 27 Access window of DQS from CK/CK# tDQSCK -0.60 +0.60 -0.75 +0.75 -0.75 +0.75 ns DQS input high pulse width tDQSH 0.35 0.35 0.35 tCK DQS input low pulse width tDQSL 0.35 0.35 0.35 tCK DQS-DQ skew, DQS to last DQ valid, per group, per access tDQSQ 0.4 0.5 0.5 ns 22, 23 Write command to first DQS latching transition tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK DQS falling edge to CK rising - setup time tDSS 0.20 0.20 0.20 tCK DQS falling edge from CK rising - hold time tDSH 0.20 0.20 0.20 tCK Half clock period tHP tCH,tCL tCH,tCL tCH,tCL ns 8 Data-out high-impedance window from CK/CK# tHZ +0.70 +0.75 +0.75 ns 16, 37 Data-out low-impedance window from CK/CK# tLZ -0.70 -0.75 -0.75 ns 16, 37 Address and control input hold time (fast slew rate) tIHF 0.75 0.90 0.90 ns 12 Address and control input setup time (fast slew rate) tISF 0.75 0.90 .900 ns 12 Address and control input hold time (slow slew rate) tIHS 0.8 1 1 ns 12 Address and control input setup time (slow slew rate) tISS 0.8 1 1 ns 12 Address and Control input pulse width (for each input) tIPW 2.2 2.2 2.2 ns LOAD MODE REGISTER command cycle time tMRD 12 15 15 ns |
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