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W3EG6433S335JD3 Datasheet(PDF) 7 Page - White Electronic Designs Corporation |
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W3EG6433S335JD3 Datasheet(HTML) 7 Page - White Electronic Designs Corporation |
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7 / 12 page  7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs W3EG6433S-D3 -JD3 November 2005 Rev. 2 PRELIMINARY DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS AC Characteristics 335 (DDR333@CL=2.5 ) 262 (DDR266@CL=2.0) 263 (DDR266@CL=2.0) 265 (DDR266@CL=2.5) Parameter Symbol Min Max Min Max Min Max Min Max Units Notes Row cycle time tRC 60 60 65 65 ns Refresh row cycle time tRFC 72 75 75 75 ns Row active time tRAS 42 70K 45 120K 45 120K 45 120K ns RAS to CAS delay tRCD 18 15 20 20 ns Row precharge time tRP 18 15 20 20 ns Row active to Row active delay tRRD 12 15 15 15 ns Write recovery time tWR 15 15 15 15 ns Last data in to Read command tWTD 1111 tCK Col. address to Col. address delay tCCD 1111 tCK Clock cycle time CL=2.0 tCK 7.5 12 7.5 12 7.5 12 10 12 ns CL=2.5 6 12 7.5 12 7.5 12 7.5 12 ns Clock high level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK Clock low level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK DQS-out access time from CK/CK tDQSCK -0.6 +0.6 -0.75 +0.75 -0.75 +0.75 -0.75 +0.75 ns Output data access time from CK/CK tAC -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 -0.75 +0.75 ns Data strobe edge to output data edge tDQSQ - 0.45 - 0.5 - 0.5 - 0.5 ns 12 Read Preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK Read Postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK CK to valid DQS-in tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK DQS-in setup time tWPRES 0000 ns 3 DQS-in hold time tWPRE 0.25 0.25 0.25 0.25 tCK DQS falling edge to CK rising-setup time tDSS 0.2 0.2 0.2 0.2 tCK DQS falling edge from Ck rising-hold time tDSH 0.2 0.2 0.2 0.2 tCK DQS-in high level width tDQSH 0.35 0.35 0.35 0.35 tCK DQS-in low level width tDQSL 0.35 0.35 0.35 0.35 tCK DQS-in cycle time tDSC 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK Address and Control Input setup time (fast) tIS 0.75 0.9 0.9 0.9 ns i,5.7~9 Address and Control Input hold time (fast) tIH 0.75 0.9 0.9 0.9 ns i,5.7~9 Address and Control Input setup time (slow) tIS 0.8 1.0 1.0 1.0 ns i,6~9 Address and Control Input setup time (slow) tIH 0.8 1.0 1.0 1.0 ns i,6~9 Data-out high impedence time from CK/CK tHZ +0.7 +0.75 +0.75 +0.75 ns 1 Data-out high impedence time from CK/CK tLZ -0.7 +0.7 -0.75 +0.75 -0.75 +0.75 -0.75 +0.75 ns 1 Input Slew Rate (for input only pins) tSL(I) 0.5 0.5 0.5 0.5 V/ns Input Slew Rate (for I/O pins) tSL(IO) 0.5 0.5 0.5 0.5 V/ns |
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