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W3EG6462S-D3 Datasheet(PDF) 5 Page - White Electronic Designs Corporation |
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W3EG6462S-D3 Datasheet(HTML) 5 Page - White Electronic Designs Corporation |
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5 / 13 page  White Electronic Designs W3EG6462S-D3 -JD3 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com May 2005 Rev. 4 ADVANCED IDD SPECIFICATIONS AND TEST CONDITIONS 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V Includes DDR SDRAM component only Parameter Symbol Conditions DDR400@ CL=3 Max DDR333@ CL=2.5-3-3 Max DDR266@ CL=2 Max DDR266@ CL=2.5 Max DDR200@ CL=2 Max Units Operating Current IDD0 One device bank; Active - Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. 2200 1960 1800 1800 1800 mA Operating Current IDD1 One device bank; Active-Read- Precharge Burst = 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle. 2480 2320 2080 2080 2080 mA Precharge Power- Down Standby Current IDD2P All device banks idle; Power-down mode; tCK=tCK (MIN); CKE=(low) 64 64 64 64 64 rnA Idle Standby Current IDD2F CS# = High; All device banks idle; tCK=tCK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. 960 800 720 720 720 mA Active Power-Down Standby Current IDD3P One device bank active; Power-Down mode; tCK (MIN); CKE=(low) 640 480 400 400 400 mA Active Standby Current IDD3N CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. 1120 960 800 800 800 mA Operating Current IDD4R Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK= TCK (MIN); lOUT = 0mA. 2720 2360 2000 2000 2000 mA Operating Current IDD4W Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle. 2680 2360 2000 2000 2000 rnA Auto Refresh Current IDD5 tRC = tRC (MIN) 3200 3000 2680 2680 2680 mA Self Refresh Current IDD6 CKE ≤ 0.2V 64 64 64 64 64 mA Operating Current IDD7A Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address and control inputs change only during Active Read or Write commands. 4880 4240 3600 3600 3600 mA |
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