W3EG128M72ETSU-D3

-JD3

-AJD3

9

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

January 2005

Rev. 0

ADVANCED

Notes

1.

2.

conducted at nominal reference/supply voltage levels, but the related specifications

and device operation are guaranteed for the full voltage range specified.

3.

Outputs measured with equivalent load:

Output

Output

(V

OUT

)

Reference

Reference

Point

Point

50Ω

50Ω

TT

30pF

30pF

4.

CK/CK#), and parameter specifications are guaranteed for the specified AC input

levels under normal use conditions. The mini-mum slew rate for the input signals

5.

The AC and DC input level specifications are as defined in the SSTL_2 Standard

(i.e., the receiver will effectively switch as a result of the signal crossing the AC

input level, and will remain in that state as long as the signal does not ring back

above [below] the DC input LOW [HIGH] level).

6.

for DC error and an additional ±25mV for AC noise. This measurement is to be

7.

8.

with mini-mum cycle time at CL = 2 for 262 and 202, CL = 2.5 for 265, 335 and

CL = 3 for 403 with the outputs open.

9.

Enables on-chip refresh and address counters.

at the defined cycle rate.

is grouped with I/O pins, reflecting the fact that they are matched in loading.

12. For slew rates < 1 V/ns and ≥ to 0.5 Vns. If the slew rate is < 0.5V/ns, timing

functionality is uncertain. For 403, slew rates must be 0.5 V/ns.

13. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at

which CK and CK# cross; the input reference level for signals other than CK/CK# is

15. The output timing reference level, as measured at the timing reference point

transitions. These parameters are not referenced to a specific voltage level, but

specify when the device output is no longer driving (HZ) or begins driving (LZ).

17. The intent of the Don’t Care state after completion of the postamble is the DQS-

driven signal should either be high, low, or high-Z and that any signal transition

within the input switching region must follow valid input requirements. That is, if

18. This is not a device limit. The device will operate with a negative value, but system

performance could be degraded due to bus turnaround.

19. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE

command. The case shown (DQS going from High-Z to logic LOW) applies when

no WRITEs were previously in progress on the bus. If a previous WRITE was in

21. The refresh period 64ms. This equates to an average refresh rate of 7.8125µs.

However, an AUTO REFRESH command must be as-serted at least once every

70.3µs; burst refreshing or posting by the DRAM controller greater than eight

refresh cycles is not allowed.

the clock duty cycle and a practical data valid window can be derived. The clock

is allowed a maximum duty cycle variation of 45/55, beyond which functionality

is uncertain. Figure 7, Derating Data Valid Window, shows derating curves are

provided below for duty cycles ranging between 50/50 and 45/55.

23. Each byte lane has a corresponding DQS.

24. This limit is actually a nominal value and does not result in a fail value. CKE is

standby).

25. To maintain a valid level, the transitioning edge of the input must:

a. Sustain a constant slew rate from the current AC level through to the target AC

b. Reach at least the target AC level.

c. After the AC target level is reached, continue to maintain at least the target DC

26. JEDEC specifies CK and CK# input slew rate must be ≥ 1V/ns (2V/ns

differentially).

27. DQ and DM input slew rates must not deviate from DQS by more than 10 percent.

If the DQ/ DM/DQS slew rate is less than 0.5 V/ns, timing must be derated: 50ps

exceeds 4 V/ns, functionality is uncertain. For 403, slew rates must be ≥ 0.5 V/ns.

29. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary

by the same amount.

CK and CK/ inputs, collectively during bank active.

31. READs and WRITEs with auto precharge are not allowed to be issued until

32. Any positive glitch in the nominal voltage must be less than 1/3 of the clock and

not more than +400mV or 2.9V maximum, whichever is less. Any negative glitch

must be less than 1/3 of the clock cycle and not exceed either -300mV or 2.2V

mini-mum, whichever is more positive.