W3EG2128M64ETSR265JD3XG datasheet(5/13 Pages) WEDC

Part #	W3EG2128M64ETSR265JD3XG

Description	2GB - 2x128Mx64 DDR SDRAM REGISTERED w/PLL

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Manufacturer	WEDC [White Electronic Designs Corporation]

Direct Link	http://www.whiteedc.com

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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

April 2005

Rev. 0

W3EG2128M64ETSR-JD3

ADVANCED

IDD SPECIFICATIONS AND TEST CONDITIONS

Recommended operating conditions, 0°C

≤ TA ≤ 70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V

Includes DDR SDRAM component only

Parameter

Symbol

Conditions

DDR333@

CL=2.5

Max

DDR266@

CL=2

Max

DDR266@

CL=2.5

Max

Units

Operating Current

IDD0

One device bank; Active - Precharge; tRC=tRC

(MIN); tCK=tCK (MIN); DQ,DM and DQS inputs

changing once per clock cycle; Address and control

inputs changing once every two cycles.

2080

1880

mA

Operating Current

IDD1

One device bank; Active-Read-Precharge Burst

= 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA;

Address and control inputs changing once per

clock cycle.

2360

2160

mA

Precharge Power-

Down Standby Current

IDD2P

All device banks idle; Power-down mode; tCK=tCK

(MIN); CKE=(low)

160

rnA

Idle Standby Current

IDD2F

CS# = High; All device banks idle; tCK=tCK (MIN);

CKE = high; Address and other control inputs

changing once per clock cycle. VIN = VREF for DQ,

DQS and DM.

1040

960

mA

Active Power-Down

Standby Current

IDD3P

One device bank active; Power-Down mode; tCK

(MIN); CKE=(low)

560

480

mA

Active Standby Current

IDD3N

CS# = High; CKE = High; One device bank; Active-

Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM

and DQS inputs changing twice per clock cycle;

Address and other control inputs changing once

per clock cycle.

800

720

mA

Operating Current

IDD4R

Burst = 2; Reads; Continuous burst; One device

bank active; Address and control inputs changing

once per clock cycle; TCK= TCK (MIN); lOUT = 0mA.

2560

2320

mA

Operating Current

IDD4W

Burst = 2; Writes; Continuous burst; One device

bank active; Address and control inputs changing

once per clock cycle; tCK=tCK (MIN); DQ,DM and

DQS inputs changing once per clock cycle.

2640

2400

rnA

Auto Refresh Current

IDD5

tRC = tRC (MIN)

3520

3360

mA

Self Refresh Current

IDD6

CKE

≤ 0.2V

144

mA

Operating Current

IDD7A

Four bank interleaving Reads (BL=4) with auto

precharge with tRC=tRC (MIN); tCK=tCK (MIN);

Address and control inputs change only during

Active Read or Write commands.

5000

4600

mA

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