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N74F846D Datasheet(PDF) 2 Page - NXP Semiconductors |
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N74F846D Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 18 page Philips Semiconductors Product specification 74F841/74F842/74F843/ 74F845/74F846 Bus interface latches 74F841/74F842 10-bit bus interface latches, non-inverting/inverting (3-State) 74F843 9-bit bus interface latch, non-inverting (3-State) 74F845/74F846 8-bit bus interface latches, non-inverting/inverting (3-State) 2 1999 Jun 23 853–1208 21851 FEATURES • High speed parallel latches • Extra data width for wide address/data paths or buses carrying parity • High impedance NPN base input structure minimizes bus loading • IIL is 20µA vs 1000A for AM29841 series • Buffered control inputs to reduce AC effects • Ideal where high speed, light loading, or increased fan-in are required as with MOS microprocessors • Positive and negative over-shoots are clamped to ground • 3-State outputs glitch free during power-up and power-down • 48mA sink current • Slim dual in-line 300 mil package • Broadside pinout • Pin-for-pin and function compatible with AMD AM29841-846 series TYPE TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT (TOTAL) 74F841, 74F842 5.5ns 60mA 74F843, 74F845 5.5ns 75mA 74F846 6.2ns 60mA DESCRIPTION The 74F841–74F846 bus interface latch series are designed to provide extra data width for wider address/data paths of buses carrying parity. The 74F841–74F846 series are funcitonally an pin compatible to the AMD AM29841–AM29846 series. The 74F841 consists of ten D-type latches with 3-State outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is High. This allows asynchronous operation, as the output transition follows the data in transition. On the LE High-to-Low transition, the data that meets the setup and hold time is latched. Data appears on the bus when the Output Enable (OE) is Low. When OE is High the output is in the High-impedance state. The 74F842 is the inverted output version of the 74F841. The 74F843 consists of nine D-type latches with 3-State outputs. In addition to the LE and OE pins, the 74F843 has a Master Reset (MR) pin and Preset (PRE) pin. These pins are ideal for parity bus interfacing in high performance systems. When MR is Low, the outputs are Low if OE is Low. When MR is High, data can be entered into the latch. When PRE is Low, the outputs are High, if OE is Low, PRE overrides MR. The 74F845 consists of eight D-type latches with 3-State outputs. In addition to the LE, OE, MR and PRE pins, the 74F845 has two addtitional OE pins making a total of three Output Enables (OE0, OE1, OE2) pins. The multiple Ouptut Enables (OE0, OE1, OE2) allow multi-user control of the interface, e.g., CS, DMA, and RD/WR. The 74F846 is the inverted output version of the 74F845. ORDERING INFORMATION PACKAGES COMMERCIAL RANGE VCC = 5V±10%; Tamb = 0°C to +70°C PACKAGE DRAWING NUMBER 24-pin plastic Slim DIP (300 mil) N74F841N, N74F842N, N74F843N, N74F845N, N74F846N SOT222-1 24-pin plastic SOL N74F841D, N74F842D, N74F843D, N74F845D, N74F846D SOT137-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS DESCRIPTION 74F(U.L.) HIGH/LOW LOAD VALUE HIGH/LOW Dn Data inputs 1.0/0.033 20 µA/20µA LE Latch Enable input 1.0/0.033 20 µA/20µA OE, OEn Output Enable input (active Low) 1.0/0.033 20 µA/20µA MR Master Reset input (active Low) 1.0/0.033 20 µA/20µA PRE Preset input (active Low) 1.0/0.033 20 µA/20µA Qn Data outputs 1200/80 24mA/48mA Qn Data outputs 1200/80 24mA/48mA NOTE: One (1.0) FAST Unit Load is defined as: 20 µA in the High state and 0.6mA in the Low state. |
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