W3E32M72S-XSBX

7

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

July 2006

Rev. 6

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

TABLE 1 - BURST DEFINITION

Burst

Length

Starting Column

Address

Order of Accesses Within a Burst

Type = Sequential

Type = Interleaved

2

A0

0

0-1

0-1

1

1-0

1-0

4

A1

A0

0

0

0-1-2-3

0-1-2-3

0

1

1-2-3-0

1-0-3-2

1

0

2-3-0-1

2-3-0-1

1

1

3-0-1-2

3-2-1-0

8

A2

A1

A0

0

0

0

0-1-2-3-4-5-6-7

0-1-2-3-4-5-6-7

0

0

1

1-2-3-4-5-6-7-0

1-0-3-2-5-4-7-6

0

1

0

2-3-4-5-6-7-0-1

2-3-0-1-6-7-4-5

0

1

1

3-4-5-6-7-0-1-2

3-2-1-0-7-6-5-4

1

0

0

4-5-6-7-0-1-2-3

4-5-6-7-0-1-2-3

1

0

1

5-6-7-0-1-2-3-4

5-4-7-6-1-0-3-2

1

1

0

6-7-0-1-2-3-4-5

6-7-4-5-2-3-0-1

1

1

1

7-0-1-2-3-4-5-6

7-6-5-4-3-2-1-0

NOTES:

1. For a burst length of two, A1-Ai select two-data-element block; A0

selects the starting column within the block.

2. For a burst length of four, A2-Ai select four-data-element block; A0-1

select the starting column within the block.

3. For a burst length of eight, A3-Ai select eight-data-element block;

A0-2 select the starting column within the block.

4. Whenever a boundary of the block is reached within a given

sequence above, the following access wraps within the block.

FIG. 3 MODE REGISTER DEFINITION

M3 = 0

2

4

8

Reserved

Reserved

Reserved

M3 = 1

2

4

8

Reserved

Reserved

Reserved

Reserved

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

0

0

Valid

Valid

0

1

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Reserved

2

Reserved

Reserved

2.5

Reserved

Burst Length

M0

0

1

0

1

0

1

0

1

Burst Length

CAS Latency

BT

Mode Register (Mx)

Address Bus

M1

0

0

1

1

0

0

1

1

M2

0

0

0

0

1

1

1

1

M3

M4

0

1

0

1

0

1

0

1

M5

0

0

1

1

0

0

1

1

M6

0

0

0

0

1

1

1

1

M6-M0

M8

M7

Operating Mode

* M14 and M13

(BA0 and BA1 must be

"0, 0" to select

the base mode register

(vs. the extended

mode register).

0*

0*

Reserved

Reserved

Reserved

Reserved

M9

M10

M11

0

0

0

10

0

0

0

--

-

-

-

-

M12

0

0

-

14

13

12 11 10

9

8

7

6

5

4

3

2

1

0

WRITE

The WRITE command is used to initiate a burst write

access to an active row. The value on the BA0, BA1 inputs

selects the bank, and the address provided on inputs A0-9

selects the starting column location. The value on input A10

determines whether or not AUTO PRECHARGE is used. If

AUTO PRECHARGE is selected, the row being accessed

will be precharged at the end of the WRITE burst; if AUTO

PRECHARGE is not selected, the row will remain open

for subsequent accesses. Input data appearing on the DQ

is written to the memory array subject to the DQM input

logic level appearing coincident with the data. If a given

DQM signal is registered LOW, the corresponding data

will be written to memory; if the DQM signal is registered

HIGH, the corresponding data inputs will be ignored, and a

WRITE will not be executed to that byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate the

open row in a particular bank or the open row in all banks.

The bank(s) will be available for a subsequent row access

issued. Except in the case of concurrent auto precharge,

where a READ or WRITE command to a different bank is

allowed as long as it does not interrupt the data transfer

in the current bank and does not violate any other timing

parameters. Input A10 determines whether one or all

banks are to be precharged, and in the case where only

one bank is to be precharged, inputs BA0, BA1 select the

bank. Otherwise BA0, BA1 are treated as “Don’t Care.”

Once a bank has been precharged, it is in the idle state and