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W3E64M72S-266BM Datasheet(PDF) 6 Page - White Electronic Designs Corporation |
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W3E64M72S-266BM Datasheet(HTML) 6 Page - White Electronic Designs Corporation |
6 / 19 page W3E64M72S-XBX 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs June 2005 Rev. 0 ADVANCED White Electronic Designs Corp. reserves the right to change products or specifications without notice. BURST TYPE Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 1. READ LATENCY The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2, 2.5, or 3 clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n+m. Table 2 below indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used as unknown operation or incompatibility with future versions may result. OPERATING MODE The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7-A12 each set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9-A12 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. Although not required, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL, it should always be followed by a LOAD MODE REGISTER command to select normal operating mode. All other combinations of values for A7-A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. EXTENDED MODE REGISTER The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable, output drive strength, and QFC. These functions are controlled via the bits shown in Figure 5. The extended mode register is programmed via the LOAD MODE REGISTER command to the mode register (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL. The extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. TABLE 2 – CAS LATENCY ALLOWABLE OPERATING FREQUENCY (MHz) SPEED CAS LATENCY = 2 CAS LATENCY = 2.5 CAS LATENCY = 3 -200 ≤ 75 ≤ 100 — -250 ≤ 100 ≤ 125 — -266 ≤ 100 ≤ 133 — -333* ≤ 100 ≤ 133/≤ 166 ≤ 166 * For 333Mbs operation of Industrial and commercial temperatures CL = 2.5, at Military temperature CL = 3. OUTPUT DRIVE STRENGTH The normal full drive strength for all outputs are specified to be SSTL2, Class II. DLL ENABLE/DISABLE When the part is running without the DLL enabled, device functionality may be altered. The DLL must be enabled for normal operation. DLL enable is required during power- up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles with CKE high must occur before a READ command can be issued. |
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