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W3E32M64S-XBX Datasheet(PDF) 4 Page - White Electronic Designs Corporation |
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W3E32M64S-XBX Datasheet(HTML) 4 Page - White Electronic Designs Corporation |
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4 / 17 page  W3E32M64S-XBX 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com White Electronic Designs July 2006 Rev. 3 RAS0# WE0# CAS0# WE# RAS# CAS# CLK0# CLK# CS0# CS# RAS1# WE1# CAS1# WE# RAS# CAS# CLK1# CLK# CS1# CS# A0-12 A0-12 BA0-1 BA0-1 DQ0 DQ15 CKE0 CKE DQML0 DQML DQMH0 DQMH DQ0 DQ15 U1 A0-12 BA0-1 DQ16 DQ31 DQ0 DQ15 U0 CKE1 CKE DQML1 DQML DQMH1 DQMH DQ0 DQ15 U2 A0-12 BA0-1 DQ32 DQ47 CKE2 CKE RAS2# WE2# CAS2# WE# RAS# CAS# CLK2# CLK# CS2# CS# DQML2 DQML DQMH2 DQMH RAS3# WE3# CAS3# DQ0 DQ15 WE# U3 RAS# A0-12 BA0-1 CLK3# CLK# CAS# DQ48 DQ63 CKE3 CKE CS3# CS# DQSL3 DQSL DQSH3 DQSH Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= Y= CLK3 CLK VREF DQSL2 DQSL DQSH2 DQSH VREF DQSL1 DQSL DQSH1 DQSH VREF DQSL0 DQSL DQSH0 DQSH CLK2 CLK CLK1 CLK CLK0 CLK VREF DQML3 DQML DQMH3 DQMH FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM detect an LVCMOS LOW level after VCC is applied. After CKE passes through VIH, it will transition to an SSTL_2 signal and remain as such until power is cycled. Maintaining an LVCMOS LOW level on CKE during power-up is required to ensure that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200µs delay prior to applying an executable command. Once the 200µs delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a LOAD MODE REGISTER command should be issued for the extended mode register (BA1 LOW and BA0 HIGH) to enable the DLL, followed by another LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL and to program the operating parameters. Two-hundred clock cycles are required between the DLL reset and any READ command. A PRECHARGE ALL command should then be applied, placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed (tRFC must be satisfied.) Additionally, a LOAD MODE REGISTER command for the mode register with the reset DLL bit deactivated (i.e., to program operating parameters without resetting the DLL) is required. Following these requirements, the DDR SDRAM is ready for normal operation. |
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