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White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

White Electronic Designs

W3DG64126V-D2

January 2005

Rev. 1

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

Notes

1.

2.

1.4V; f = 1 MHz.

3.

with mini-mum cycle time and the outputs open.

4.

Enables on-chip refresh and address counters.

5.

The minimum specifications are used only to indicate cycle time at which proper

operation over the full temperature range is ensured.

6.

An initial pause of 100µs is required after power-up, followed by two AUTO

two AUTO REFRESH command wake-ups should be repeated any time the tREF

refresh requirement is exceeded.

7.

8.

In addition to meeting the transition rate specification, the clock and CKE must

9.

Outputs measured at 1.5V with equivalent load:

Q

50pF

High-Z.

crossover point. If the input transition time is longer than 1ns, then the timing is

12. Other input signals are allowed to transition no more than once every two clocks

cycle rate.

minimum cycle rate.

17. Required clocks are specified by JEDEC functionality and are not dependent on

any timing parameter.

frequency alteration for the test condition.

19. Address transitions average one transition every two clocks.

20. CLK must be toggled a minimum of two times during this period.

for a pulse width ≤ 3ns.

23. The clock frequency must remain constant (stable clock is defined as a signal

cycling within timing constraints specified for the clock pin) during access or

CKE may be used to reduce the data rate.

7.5ns for 7.5 and 7.5ns for 10 after the first clock delay, after the last WRITE is

executed. May not exceed limit set for precharge mode.

25. Precharge mode only.

26. JEDEC and PC133, PC100 specify three clocks.

28. Parameter guaranteed by design.