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EM6622WS27 Datasheet(PDF) 9 Page - EM Microelectronic - MARIN SA |
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EM6622WS27 Datasheet(HTML) 9 Page - EM Microelectronic - MARIN SA |
9 / 70 page EM6622 03/02 REV. C/445 Copyright 2002, EM Microelectronic-Marin SA 9 www.emmicroelectronic.com 4.1 Oscillation Detection Circuit At power on, the voltage regulator starts to follow the supply voltage and triggers the power on reset circuitry, and thus the system reset. The CPU of the EM6622 remains in the reset state for the ‘CPU Reset Delay’, to allow the oscillator to stabilize after power up. The oscillator is disabled during sleep mode. So when waking up from sleep mode, the CPU of the EM6622 remains in the reset state for the CPU Reset Delay, to allow the oscillator to stabilize. During this time, the Oscillation Detection Circuit is inhibited. In active or standby modes, the oscillator detection circuit monitors the oscillator. If it stops for any reason, a system reset is generated. After clock restart the CPU waits for the CPU Reset Delay before executing the first instructions. The oscillation detection circuitry can be inhibited with bit NoOscWD = 1 in register RegVldCntl. At power up, and after any system reset, the function is activated. The ‘CPU Reset Delay’ is 32768 system clocks ( Ck[16] ) long. Figure 6. Reset Structure System Reset Delay CPU Reset Delay Enable Activate Digital W atchdog O scillation Detection Reset from Port A Input Com bination Reset PAD Sleep OptInpRSleep Reset CPU Inhibit Oscillation Detection Inhibit Digital W atchdog PO R POR to O ption Registers & SleepEn Latch DEBOUNCE Sleep Latch SleepEn Latch POR Internal Data Bus Write Reset Read Status Write Active Read Status Ck[10] Ck[1] Ck[8] Ck[1] Ck[15] POR Analogue Filter |
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