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STM6315SDW13F Datasheet(PDF) 8 Page - STMicroelectronics |
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STM6315SDW13F Datasheet(HTML) 8 Page - STMicroelectronics |
8 / 21 page Operation STM6315 8/21 2.4 Valid RST Output Down to VCC = 0V When VCC falls below 1V, the RST output no longer sinks current, but becomes an open circuit. In most systems this is not a problem, as most MCUs do not operate below 1V. However, in applications where RST output must be valid down to 0V, a pull-down resistor may be added to hold the RST output low. This resistor must be large enough to not load the RST output, and still be small enough to pull the output to Ground. A 100K Ω resistor is recommended. Figure 5. Reset Timing Diagram Figure 6. Manual Reset Timing Diagram, Switch Bounce/Debounce AI11166 RST VCC VRST VCC (min) trec AI11167b RST MR trec MR-to-RST Delay MR Glitch Rejection MR Input Pulse Width |
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