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W83176G-733 Datasheet(PDF) 8 Page - Winbond |
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W83176G-733 Datasheet(HTML) 8 Page - Winbond |
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8 / 14 page  DUAL BANK DDR BUFFER FOR VIA CHIPSET Publication Release Date: March, 2006 - 5 - Revision 1.0 W83176R-733/W83176G-733 7.4 REGISTER 8 ~ Register 17 RESERVED 7.5 Skew step reference Table SKEW<2:0>/<1:0> DELAY TIME (PS) 000 0 001 250 010 500 011 750 100 1000 101 1250 110 1500 111 1750 7.6 Register 18: Skew Control (Default: 88h) BIT NAME PWD DESCRIPTION 7 Reserved 1 Reserved 6 DDRA_TSKEW<2> 0 5 DDRA_TSKEW<1> 0 4 DDRA_TSKEW<0> 0 DDRA True clock outputs with FB_OUTA True clock SKEW control bits 3 Reserved 1 Reserved 2 DDRA_CSKEW<2> 0 1 DDRA_CSKEW<1> 0 0 DDRA_CSKEW<0> 0 DDRA Complementary clock outputs with FB_OUTA True clock SKEW control bits 7.7 Register 19: Skew Control (Default: 80h) BIT NAME PWD DESCRIPTION 7 Reserved 1 Reserved 6 DDRB_CSKEW<2> 0 5 DDRB_CSKEW<1> 0 4 DDRB_CSKEW<0> 0 DDRB Complementary clock outputs with FB_OUTB True clock SKEW control bits 3 FAOUT_SKEW<1> 0 2 FAOUT_SKEW<0> 0 FB_OUTA, DDRA clock outputs with BUF_INA clock SKEW control bits 1 FBOUT_SKEW<1> 0 0 FBOUT_SKEW<0> 0 FB_OUTB, DDRB clock outputs with BUF_INB clock SKEW control bits |
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