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EDI416S4030A12SI Datasheet(PDF) 10 Page - White Electronic Designs Corporation

Part # EDI416S4030A12SI
Description  1Mx16 Bits x 4 Banks Synchronous DRAM
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Manufacturer  WEDC [White Electronic Designs Corporation]
Direct Link  http://www.whiteedc.com
Logo WEDC - White Electronic Designs Corporation

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EDI416S4030A
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
January, 2003
Rev. 2
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
Current
State
Command
Action
Notes
CE# RAS# CAS# WE#
BA
A11, A10/AP-A0
Description
Write
Recovering
with Auto
Precharge
L
L
L
L
OP Code
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
ILLEGAL
4
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
4
L
H
L
L
BA
Column
Write
ILLEGAL
4,9
L
H
L
H
BA
Column
Read
ILLEGAL
4,9
L
H
H
L
X
X
Burst Termination
No Operation; Precharge after tDPL
L
H
H
H
X
X
No Operation
No Operation; Precharge after tDPL
H
X
X
X
X
X
Device Deselect
No Operation; Precharge after tDPL
Refreshing
L
L
L
L
OP Code
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
ILLEGAL
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
L
H
L
L
BA
Column
Write
ILLEGAL
L
H
L
H
BA
Column
Read
ILLEGAL
L
H
H
L
X
X
Burst Termination
No Operation; idle after tRC
L
H
H
H
X
X
No Operation
No Operation; idle after tRC
H
X
X
X
X
X
Device Deselect
No Operation; idle after tRC
Mode
Register
Accessing
L
L
L
L
OP Code
Mode Register Set
ILLEGAL
L
L
L
H
X
X
Auto or Self Refresh
ILLEGAL
L
L
H
L
X
X
Precharge
ILLEGAL
L
L
H
H
BA
Row Address
Bank Activate
ILLEGAL
L
H
L
L
BA
Column
Write
ILLEGAL
L
H
L
H
BA
Column
Read
ILLEGAL
L
H
H
L
X
X
Burst Termination
ILLEGAL
L
H
H
H
X
X
No Operation
No Operation; Idle after two clock cycles
H
X
X
X
X
X
Device Deselect
No Operation; Idle after two clock cycles
CURRENT STATE TRUTH TABLE (CONT.)
NOTES:
1.
CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the command is being applied to.
2.
All Banks must be idle otherwise it is an illegal action.
3.
If CKE is active (high) the SDRAM starts the Auto (CBR) Refresh operation, if CKE is inactive (low) then the Self Refresh mode is entered.
4.
The Current State refers only to one of the banks, if BA0, BA1 selects this bank then the action is illegal. If BA0, BA1 selects the bank not being referenced by the Current State
then the action may be legal depending on the state of that bank.
5.
If CKE is inactive (low) then the Power Down mode is entered, otherwise there is a No Operation.
6.
The minimum and maximum Active time (tRAS) must be satisfied.
7.
The RAS# to CAS# Delay (tRCD) must occur before the command is given.
8.
Address A10 is used to determine if the Auto Precharge function is activated.
9.
The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. The command is illegal if the minimum bank to bank delay time (tRRD) is not
satisfied.


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