SM8761AAS datasheet(6/11 Pages) NPC

Part #	SM8761AAS

Description	Spread Spectrum Clock Generator

Download	11 Pages

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Manufacturer	NPC [Nippon Precision Circuits Inc]

Direct Link	http://www.npc.co.jp/en

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6 / 11 page

SM8761 series

NIPPON PRECISION CIRCUITS INC.—6

AC Characteristics

SM8761AA

VDD = 3.3 ± 0.3V, VSS = 0V, Ta = −20 to +80°C unless otherwise noted.

SM8761AB

VDD = 3.3 ± 0.3V, VSS = 0V, Ta = −20 to +80°C unless otherwise noted.

Parameter

Symbol

Pins

Condition

Rating

Unit

min

typ

max

Clock frequency

fin

XT

Crystal connection

20

–

40

MHz

External clock input*1

*1. When using an external clock input, it is recommended that the clock on XT have 50% duty and VDD level signal amplitude. Note that the input signal

voltage must not exceed the absolute maximum rating, otherwise it may cause the device to breakdown.

20

–

108

Output clock rise time*2

*2. Measured using the circuit in Figure 1 on the NPC standard evaluation board.

tr

CLKOUT

CL = 15pF, VOL = 0.2VDD to VOH =

0.8VDD transition time

–

2.0

–

ns

Output clock fall time*2

tf

CLKOUT

CL = 15pF, VOH = 0.8VDD to VOL =

0.2VDD transition time

–

2.0

–

ns

Output clock jitter*2

tjitter

CLKOUT

Cycle-to-cycle jitter,

Ta = 25

°C, CL = 15pF,

VO = 0.5VDD

ﬁn = 33MHz

–

200

–

ps

ﬁn = 75MHz

–

120

–

Output clock duty cycle*2

Dt

CLKOUT

Ta = 25

°C, CL = 15pF, VO = 0.5VDD

45

50

55

%

Power-up time*2,*3

*3. The power-up time is the time from when the supply reaches 3.0V after the supply is turned ON until each output clock reaches its designated fre-

quency to within ± 0.1%.

tp

CLKOUT

–

1

5

ms

Parameter

Symbol

Pins

Condition

Rating

Unit

min

typ

max

Clock frequency

fin

XT

Crystal connection

12

–

32

MHz

External clock input*1

*1. When using an external clock input, it is recommended that the clock on XT have 50% duty and VDD level signal amplitude. Note that the input signal

voltage must not exceed the absolute maximum rating, otherwise it may cause the device to breakdown.

12–32

Output clock rise time*2

*2. Measured using the circuit in Figure 1 on the NPC standard evaluation board.

tr

CLKOUT

CL = 15pF, VOL = 0.2VDD to VOH =

0.8VDD transition time

–

2.0

–

ns

Output clock fall time*2

tf

CLKOUT

CL = 15pF, VOH = 0.8VDD to VOL =

0.2VDD transition time

–

2.0

–

ns

Output clock jitter*2

tjitter

CLKOUT

Cycle-to-cycle jitter,

Ta = 25

°C, CL = 15pF,

VO = 0.5VDD

ﬁn = 12MHz

–

450

–

ps

ﬁn = 16MHz

–

200

–

ﬁn = 20MHz

–

300

–

ﬁn = 27MHz

–

180

–

Output clock duty cycle*2

Dt

CLKOUT

Ta = 25

°C, CL = 15pF, VO = 0.5VDD

45

50

55

%

Power-up time*2,*3

*3. The power-up time is the time from when the supply reaches 3.0V after the supply is turned ON until each output clock reaches its designated fre-

quency to within ± 0.1%.

tp

CLKOUT

–

1

5

ms

Figure 1. Measurement circuit

Frequency &

Time Interval

Analyzer

(HP5371A)

X'tal

Oscilloscope

(Infinium

HP54845A)

Passive Probe

(HP10435A)

Active Probe

(HP1152A)

DUT

Jitter

Measurement

System

(ASA, M1)

+

DUT: Device Under Testing

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