EDI2AG272128V-D1

White Electronic Designs

7

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

July 1999

ADVANCED

White Electronic Designs Corp. reserves the right to change products or specifications without notice.

READ CYCLE TIMING PARAMETERS

BURST ADDRESS TABLE (MODE=GND)

SYNCHRONOUS ONLY READ CYCLE

First

Address

(external)

Second

Address

(internal)

Third

Address

(internal)

Fourth

Address

(internal)

A-A00

A-A01

A-A10

A-A11

A-A01

A-A00

A-A11

A-A10

A-A10

A-A11

A-A00

A-A01

A-A11

A-A10

A-A01

A-A00

Description

Sym

8.5ns

Min

Max

9ns

Min

Max

10ns

Min

Max

12ns

Min

Max

Units

Clock Cycle Time

*

*

10

12

15

ns

Clock High Time

*

*

455

ns

Clock Low Time

*

*

455

ns

Clock to Output Valid

**

9

10

12

ns

Clock to Output Invalid

*

*

333

ns

Clock to Output Low-Z

*

*

222

ns

Output Enable to Output Valid

*

*

445

ns

Output Enable to Output Low-Z

*

*

000

ns

Output Enable to Output High-Z

*

*

445

ns

Address Setup

*

*

2.5

2.5

2.5

ns

Bank Enable Setup

*

*

2.5

2.5

2.5

ns

Address Hold

*

*

1.0

1.0

1.0

ns

Bank Enable Hold

*

*

1.0

1.0

1.0

ns

DQ

Read Cycle

Q(Addr 1)

Q(Addr 1)

Q(Addr 2)

GW#

G#

ADDR

Ex#

CK

Addr 1

Addr 2

Addr 1

Back to Back Read

*TBD

First

Address

(external)

Second

Address

(internal)

Third

Address

(internal)

Fourth

Address

(internal)

A-A00

A-A01

A-A10

A-A11

A-A01

A-A10

A-A11

A-A00

A-A10

A-A11

A-A00

A-A01

A-A11

A-A00

A-A01

A-A10