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XX1000-QT-EV1 Datasheet(PDF) 5 Page - Mimix Broadband |
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XX1000-QT-EV1 Datasheet(HTML) 5 Page - Mimix Broadband |
5 / 7 page Page 5 of 7 Pin 3 5 6 7 10 13 15 Description RF In Vg1 Vss Vg2 RF Out Vd2 Vd1 Mimix Broadband, Inc., 10795 Rockley Rd., Houston, Texas 77099 Tel: 281.988.4600 Fax: 281.988.4615 mimixbroadband.com Characteristic Data and Specifications are subject to change without notice. ©2006 Mimix Broadband, Inc. Export of this item may require appropriate export licensing from the U.S. Government. In purchasing these parts, U.S. Domestic customers accept their obligation to be compliant with U.S. Export Laws. 7.5-22.5/15.0-45.0 GHz Active Doubler QFN, 3x3 mm App Note [1] Biasing - It is recommended to separately bias each doubler stage with Vd(1,2)=5.0V with Id1=80mA and Id2=140mA and Vss=-5.0V with Iss=50mA. XX1000-QT provides good performance at reduced bias with Vss=-2.0V and Iss=25mA. Maximum output power is achieved with Vss=-5.0V and Iss=50mA. Separate biasing is recommended if the doubler is to be used at high levels of saturation, where gate rectification will alter the effective gate control voltage. It is also recommended to use active biasing to keep the currents constant as the RF power and temperature vary; this gives the most reproducible results. Depending on the supply voltage available and the power dissipation constraints, the bias circuit may be a single transistor or a low power operational amplifier, with a low value resistor in series with the drain supply used to sense the current. The gate of the pHEMT is controlled to maintain correct drain current and thus drain voltage. The typical gate voltages needed to do this are Vg1=-0.6V and Vg2=0.0V. Typically the gate is protected with Silicon diodes to limit the applied voltage. Also, make sure to sequence the applied voltage to ensure negative gate bias is available before applying the positive drain supply. MTTFTables (TBD) These numbers were calculated based on accelerated life test information and thermal model analysis received from the fabricating foundry. Backplate Temperature 55 deg Celsius 75 deg Celsius 95 deg Celsius Channel Temperature deg Celsius deg Celsius deg Celsius FITs E+ E+ E+ MTTF Hours E+ E+ E+ Rth C/W C/W C/W Bias Conditions: Vd1=Vd2=4.0V, Id1=40 mA, Id2=140 mA, Vss=-5.0V, Iss=50mA X1000-QT April 2006 - Rev 28-Apr-06 Functional Schematic Top View |
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