Philips Semiconductors

Product specification

74F50728

Synchronizing cascaded dual positive

edge-triggered D-type flip-flop

2

September 14, 1990

853-1389 00421

FEATURES

flip-flop

edge-triggered set and reset

DESCRIPTION

The 74F50728 is a cascaded dual positive edge–triggered D–type

featuring individual data, clock, set and reset inputs; also true and

complementary outputs.

Set (SDn) and reset (RDn) are asynchronous active low inputs and

operate independently of the clock (CPn) input. They set and reset

both flip–flops of a cascaded pair simultaneously. Data must be

stable just one setup time prior to the low–to–high transition of the

clock for guaranteed propagation delays.

Clock triggering occurs at a voltage level and is not directly related

to the transition time of the positive–going pulse. Following the hold

time interval, data at the Dn input may be changed without affecting

the levels of the output. Data entering the 74F50728 requires two

clock cycles to arrive at the outputs.

The 74F50728 is designed so that the outputs can never display a

metastable state due to setup and hold time violations. If setup time

and hold time are violated the propagation delays may be extended

beyond the specifications but the outputs will not glitch or display a

metastable state. Typical metastability parameters for the 74F50728

are:

function of the rate at which a latch in a metastable state resolves

the propensity of a latch to enter a metastable state.

TYPE

TYPICAL SUPPLY

CURRENT (TOTAL)

74F50728

145 MHz

23mA

ORDERING INFORMATION

ORDER CODE

COMMERCIAL RANGE

INDUSTRIAL RANGE

DESCRIPTION

PKG DWG #

14–pin plastic DIP

N74F50728N

I74F50728N

SOT27-1

14–pin plastic SO

N74F50728D

I74F50728D

SOT108-1

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

PINS

DESCRIPTION

74F (U.L.) HIGH/

LOW

LOAD VALUE HIGH/

LOW

D0, D1

Data inputs

1.0/0.417

20

µA/250µA

CP0, CP1

Clock inputs (active rising edge)

1.0/1.0

20

µA/20µA

SD0, SD1

Set inputs (active low)

1.0/1.0

20

µA/20µA

RD0, RD1

Reset inputs (active low)

1.0/1.0

20

µA/20µA

Q0, Q1, Q0, Q1

Data outputs

50/33

1.0mA/20mA

NOTE: One (1.0) FAST unit load is defined as: 20

µA in the high state and 0.6mA in the low state.