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COP245C Datasheet(PDF) 8 Page - National Semiconductor (TI) |
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COP245C Datasheet(HTML) 8 Page - National Semiconductor (TI) |
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8 / 24 page  Functional Description (Continued) 4 All successive transfer of control instructions and suc- cessive LBIs have been completed (eg if the main program is executing a JP instruction which transfers program control to another JP instruction the interrupt will not be acknowledged until the second JP instruc- tion has been executed) c Upon acknowledgement of an interrupt the skip logic status is saved and later restored upon popping of the stack For example if an interrupt occurs during the exe- cution of ASC (Add with Carry Skip on Carry) instruction which results in carry the skip logic status is saved and program control is transferred to the interrupt servicing routine at hex address 0FF At the end of the interrupt routine a RET instruction is executed to pop the stack and return program control to the instruction following the original ASC At this time the skip logic is enabled and skips this instruction because of the previous ASC carry Subroutines should not be nested within the interrupt service routine since their popping of the stack will en- able any previously saved main program skips interfering with the orderly execution of the interrupt routine d The instruction at hex address 0FF must be a NOP e An LEI instruction may be put immediately before the RET instruction to re-enable interrupts INITIALIZATION The internal reset logic will initialize the device upon power- up if the power supply rise time is less than 1 ms and if the operating frequency at CKI is greater than 32 kHz other- wise the external RC network shown in Figure 4 must be connected to the RESET pin (the conditions in Figure 4 must be met) The RESET pin is configured as a Schmitt trigger input If not used it should be connected to VCC Initialization will occur whenever a logic ‘‘0’’ is applied to the RESET input providing it stays low for at least three instruc- tion cycle times Note If CKI clock is less than 32 kHz the internal reset logic (option 29e1) MUST be disabled and the external RC circuit must be used TLDD8422 – 6 FIGURE 4 Power-Up Circuit Upon initialization the PC register is cleared to 0 (ROM ad- dress 0) and the A B C D EN IL T and G registers are cleared The SKL latch is set thus enabling SK as a clock output Data Memory (RAM) is not cleared upon initializa- tion The first instruction at address 0 must be a CLRA (clear A register) TIMER There are two modes selected by mask option a Time-base counter In this mode the instruction cycle fre- quency generated from CKI passes through a 2-bit divide- by-4 prescaler The output of this prescaler increments the 8-bit T counter thus providing a 10-bit timer The pre- scaler is cleared during execution of a CAMT instruction and on reset For example using a 358 MHz crystal with a divide-by-16 option the instruction cycle frequency of 22370 kHz in- crements the 10-bit timer every 447 ms By presetting the counter and detecting overflow accurate timeouts be- tween 1788 ms (4 counts) and 4577 ms (1024 counts) are possible Longer timeouts can be achieved by accu- mulating under software control multiple overflows b External event counter In this mode a low-going pulse (‘‘1’’ to ‘‘0’’) at least 2 instruction cycles wide on the IN2 input will increment the 8-bit T counter Note The IT instruction is not allowed in this mode TLDD8422 – 7 Crystal or Resonator Crystal Component Values Value R1 R2 C1(pF) C2(pF) 32 kHz 220k 20M 30 6 – 36 455 kHz 5k 10M 80 40 2096 MHz 2k 1M 30 6 – 36 36 MHz 1k 1M 30 6 – 36 RC Controlled Oscillator RC Cycle VCC Time 30k 82 pF 6 – 18 ms t 45V Note 15ksRs150k 50 pFsCs150 pF FIGURE 5 Oscillator Component Values 8 |
Similar Part No. - COP245C |
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Similar Description - COP245C |
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