K4X56323PG - 7(8)E/G

January 2006

Mobile-DDR SDRAM

8M x32 Mobile-DDR SDRAM

FEATURES

• 1.8V power supply, 1.8V I/O power

• Double-data-rate architecture; two data transfers per clock cycle

• Bidirectional data strobe(DQS)

• Four banks operation

• Differential clock inputs(CK and CK)

• MRS cycle with address key programs

- CAS Latency ( 2, 3 )

- Burst Length ( 2, 4, 8, 16 )

- Burst Type (Sequential & Interleave)

- Partial Self Refresh Type ( Full, 1/2, 1/4 Array )

- Output Driver Strength Control ( Full, 1/2, 1/4, 1/8 )

• Internal Temperature Compensated Self Refresh

• Deep Power Down Mode

• All inputs except data & DM are sampled at the positive going edge of the system clock(CK).

• Data I/O transactions on both edges of data strobe, DM for masking.

• Edge aligned data output, center aligned data input.

• No DLL; CK to DQS is not synchronized.

• DM0 - DM3 for write masking only.

• Auto refresh duty cycle

- 15.6us for -25 to 85

°C

Address configuration

- DM is internally loaded to match DQ and DQS identically.

Organization

Bank

Row

Column

8M x32

BA0,BA1

A0 - A11

A0 - A8

Operating Frequency

Note :

1. CAS Latency

DDR266

DDR222

83Mhz

66Mhz

133Mhz

111Mhz

Ordering Information

- 7(8)E

90FBGA Pb(Pb Free), Normal Power, Extended Temperature(-25

°C ~ 85 °C)

- 7(8)G : 90 FBGA Pb(Pb Free), Low Power, Extended Temperature(-25

°C ~ 85 °C)

- C3/CA : 133MHz(CL=3)/111MHz(CL=3)

Part No.

Max Freq.

Interface

Package

K4X56323PG-7(8)E/GC3

133MHz(CL=3),83MHz(CL=2)

LVCMOS

90FBGA

Pb (Pb Free)

K4X56323PG-7(8)E/GCA

111MHz(CL=3),66MHz(CL=2)

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