9

Rev. B

05/10/06

IS63WV1024BLL

IS64WV1024BLL

-12 ns

-15 ns

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

Write Cycle Time

12

—

15

—

ns

CE to Write End

9

—10

—

ns

Address Setup Time to

9

—10

—

ns

Write End

Address Hold from

0

—

0

—

ns

Write End

Address Setup Time

0

—

0

—

ns

1

(1)

WE Pulse Width (OE High)

9

—10

—

ns

2

(2)

WE Pulse Width (OE Low)

11

—

12

—

ns

Data Setup to Write End

9

—

9

—ns

Data Hold from Write End

0

—

0

—

ns

WE LOW to High-Z Output

—

6

—

7

ns

WE HIGH to Low-Z Output

3

—

3

—

ns

Notes:

1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.25V, input pulse levels of 0.4V to

2. Tested with the loading specified in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3. The internal write time is defined by the overlap of

CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but

any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of

the signal that terminates the Write.

AC WAVEFORMS

DATA UNDEFINED

VALID ADDRESS

HIGH-Z

ADDRESS

CE

WE

CE_WR1.eps