1

Rev. B

02/24/05

IS62WV51216ALL

IS62WV51216BLL

Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability

arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any

published information and before placing orders for products.

512K x 16 LOW VOLTAGE,

ULTRA LOW POWER CMOS STATIC RAM

FEATURES

• High-speed access time: 45ns, 55ns

• CMOS low power operation

– 36 mW (typical) operating

– 12 µW (typical) CMOS standby

• TTL compatible interface levels

• Single power supply

• Fully static operation: no clock or refresh

required

• Three state outputs

• Data control for upper and lower bytes

• Industrial temperature available

• Lead-free available

DESCRIPTION

The

speed, 8M bit static RAMs organized as 512K words by 16

bits. It is fabricated using

technology. This highly reliable process coupled with

innovative circuit design techniques, yields high-

performance and low power consumption devices.

When

CS1 is HIGH (deselected) or when CS2 is LOW

(deselected) or when

CS1 is LOW, CS2 is HIGH and both

LB and UB are HIGH, the device assumes a standby mode

at which the power dissipation can be reduced down with

CMOS input levels.

Easy memory expansion is provided by using Chip Enable

and Output Enable inputs. The active LOW Write Enable

(WE) controls both writing and reading of the memory. A

data byte allows Upper Byte

(UB) and Lower Byte (LB)

access.

TheIS62WV51216ALLandIS62WV51216BLLarepackaged

in the JEDEC standard 48-pin mini BGA (7.2mm x 8.7mm)

and 44-Pin TSOP (TYPE II).

FUNCTIONAL BLOCK DIAGRAM

FEBRUARY 2005

A0-A18

CS1

OE

WE

512K x 16

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

I/O

DATA

CIRCUIT

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

UB

LB

CS2