1

Rev. C

02/03/06

Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability

arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any

published information and before placing orders for products.

IS61WV12816BLL

IS64WV12816BLL

FEATURES

• High-speed access time:

12 ns: 3.3V + 10%

15 ns: 2.5V-3.6V

• Operating Current: 25mA (typ.)

• Stand by Current: 400µA(typ.)

• TTL and CMOS compatible interface levels

• Fully static operation: no clock or refresh

required

• Three state outputs

• Data control for upper and lower bytes

• Industrial and Automotive temperatures avail-

able

• Lead-free available

128K x 16 HIGH-SPEED CMOS STATIC RAM

DESCRIPTION

The

high-speed, 2,097,152-bit static RAM organized as 131,072

words by 16 bits. They are fabricated using

performance CMOS technology. This highly reliable process

coupled with innovative circuit design techniques, yields

access times as fast as 12 ns with low power consumption.

When

CE is HIGH (deselected), the device assumes a

standby mode at which the power dissipation can be

reduced down with CMOS input levels.

Easy memory expansion is provided by using Chip Enable

and Output Enable inputs,

CE and OE. The active LOW

Write Enable (

WE) controls both writing and reading of the

memory. A data byte allows Upper Byte (

UB) and Lower

Byte (

LB) access.

TheIS61WV12816BLLandIS64WV12816BLLarepackaged

in the JEDEC standard 44-pin TSOP (Type II) and 48-pin

mini BGA (6mm x 8mm).

FUNCTIONAL BLOCK DIAGRAM

FEBRUARY 2006

A0-A16

CE

OE

WE

128Kx16

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VDD

I/O

DATA

CIRCUIT

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

UB

LB