IS61NVVP51236-250B datasheet(11/29 Pages) ISSI

Part #	IS61NVVP51236-250B

Description	256K x 72 and 512K x 36, 18Mb PIPELINE (NO WAIT) STATE BUS SRAM

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Manufacturer	ISSI [Integrated Silicon Solution, Inc]

Direct Link	http://www.issi.com

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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774

11

ADVANCED INFORMATION Rev. 00A

07/17/02

IS61NVVP25672

IS61NVVP51236

ISSI®

READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)

-250

-200

Symbol

Parameter

Min. Max.

Unit

fmax

Clock Frequency

—

250

—

200

MHz

tKC

Cycle Time

4.0

—

5

—

ns

tKH

Clock High Time

1.7

—

2

—

ns

tKL

Clock Low Time

1.7

—

2

—

ns

tKQ

Clock Access Time

—

2.6

—

3.0

ns

tKQX(2)

Clock High to Output Invalid

0.8

—

1.5

—

ns

tKQLZ(2,3)

Clock High to Output Low-Z

0.8

—

1

—

ns

tKQHZ(2,3)

Clock High to Output High-Z

—

2.6

—

3.0

ns

tOEQ

Output Enable to Output Valid

—

2.6

—

3.0

ns

tOELZ(2,3)

Output Enable to Output Low-Z

0

—

0

—

ns

tOEHZ(2,3)

Output Disable to Output High-Z

—

2.6

—

3.0

ns

tAS

Address Setup Time

1.0

—

1.2

—

ns

tWS

Read/Write Setup Time

1.0

—

1.2

—

ns

tCES

Chip Enable Setup Time

1.0

—

1.2

—

ns

tSE

Clock Enable Setup Time

1.0

—

1.2

—

ns

tADVS

Address Advance Setup Time

1.0

—

1.2

—

ns

tDS

Data Setup Time

1.0

—

1.2

—

ns

tAH

Address Hold Time

0.5

—

0.5

—

ns

tHE

Clock EnableHold Time

0.5

—

0.5

—

ns

tWH

Write Hold Time

0.5

—

0.5

—

ns

tCEH

Chip Enable Hold Time

0.5

—

0.5

—

ns

tADVH

Address Advance Hold Time

0.5

—

0.5

—

ns

tDH

Data Hold Time

0.5

—

0.5

—

ns

tPDS

ZZ High to Power Down

—

2

—

2

cyc

tPUS

ZZ Low to Power Down

—

2

—

2

cyc

Notes:

1. Configuration signal MODE is static and must not change during normal operation.

2. Guaranteed but not 100% tested. This parameter is periodically sampled.

3. Tested with load in Figure 2.

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IS61NVVP51236-250B Datasheet(PDF) 11 Page - Integrated Silicon Solution, Inc

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