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IS61QDB22M18 Datasheet(PDF) 6 Page - Integrated Silicon Solution, Inc |
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IS61QDB22M18 Datasheet(HTML) 6 Page - Integrated Silicon Solution, Inc |
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6 / 27 page  6 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 06/29/06 ISSI® 36 Mb (1M x 36 & 2M x 18) QUAD (Burst of 2) Synchronous SRAMs Power-Up and Power-Down Sequences The power supplies must be powered up in the following order: 1. VDD 2. VDDQ 3. VREF 4. Inputs The power-down sequence must be the reverse. VDDQ can be allowed to exceed VDD by no more than 0.6V. Application Example 2M x 18 SA R W BW0 BW1 CC KK D0–17 Q0–17 ZQ SRAM #4 R=250 Ω Vt Data-In 0–71 Data-Out 0–71 Address 0–79 R W BW0–7 Memory Controller Return CLK Source CLK Return CLK Source CLK SA R W BW0 BW1 CC KK D0–17 Q0–17 ZQ SRAM #1 R=250 Ω Vt Vt R Vt Vt R=50 Ω Vt=VREF R |
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