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IS61NLF25618A-7.5B3 Datasheet(PDF) 8 Page - Integrated Silicon Solution, Inc

Part # IS61NLF25618A-7.5B3
Description  128K x 36 and 256K x 18 4Mb, FLOW THROUGH (NO WAIT) STATE BUS SRAM
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Manufacturer  ISSI [Integrated Silicon Solution, Inc]
Direct Link  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS61NLF25618A-7.5B3 Datasheet(HTML) 8 Page - Integrated Silicon Solution, Inc

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Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00A
08/26/05
IS61NLF12836A/IS61NVF12836A
IS61NLF25618A/IS61NVF25618A
ISSI®
PIN CONFIGURATION
100-Pin TQFP
256K x 18
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100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
NC
NC
VDDQ
Vss
NC
DQPa
DQa
DQa
Vss
VDDQ
DQa
DQa
Vss
NC
VDD
ZZ
DQa
DQa
VDDQ
Vss
DQa
DQa
NC
NC
Vss
VDDQ
NC
NC
NC
NC
NC
NC
VDDQ
Vss
NC
NC
DQb
DQb
Vss
VDDQ
DQb
DQb
NC
VDD
NC
Vss
DQb
DQb
VDDQ
Vss
DQb
DQb
DQPb
NC
Vss
VDDQ
NC
NC
NC
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100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
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DQPb
DQb
DQb
VDDQ
Vss
DQb
DQb
DQb
DQb
Vss
VDDQ
DQb
DQb
Vss
NC
VDD
ZZ
DQa
DQa
VDDQ
Vss
DQa
DQa
DQa
DQa
Vss
VDDQ
DQa
DQa
DQPa
DQPc
DQc
DQc
VDDQ
Vss
DQc
DQc
DQc
DQc
Vss
VDDQ
DQc
DQc
NC
VDD
NC
Vss
DQd
DQd
VDDQ
Vss
DQd
DQd
DQd
DQd
Vss
VDDQ
DQd
DQd
DQPd
128K x 36
PIN DESCRIPTIONS
A0, A1
Synchronous Address Inputs. These
pins must tied to the two LSBs of the
address bus.
A
Synchronous Address Inputs
CLK
Synchronous Clock
ADV
Synchronous Burst Address Advance
BWa-BWd
Synchronous Byte Write Enable
WE
Write Enable
CKE
Clock Enable
Vss
Ground for Core
NC
Not Connected
CE, CE2, CE2 Synchronous Chip Enable
OE
Output Enable
DQa-DQd
Synchronous Data Input/Output
DQPa-DQPd
Parity Data I/O
MODE
Burst Sequence Selection
VDD
+3.3V/2.5V Power Supply
VSS
Ground for output Buffer
VDDQ
Isolated Output Buffer Supply: +3.3V/2.5V
ZZ
Snooze Enable


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