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IS61DDB22M18 Datasheet(PDF) 6 Page - Integrated Silicon Solution, Inc |
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IS61DDB22M18 Datasheet(HTML) 6 Page - Integrated Silicon Solution, Inc |
6 / 25 page 6 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 2/22/05 ISSI® 36 Mb (1M x 36 & 2M x 18) DDR-II (Burst of 2) CIO Synchronous SRAMs Depth Expansion The following figure depicts an implementation of four 2M x 18 DDR -II SRAMs with common I/Os. In this appli- cation example, the second pair of C and C clocks is delayed such that the return data meets the data setup and hold times at the bus master. Power-Up and Power-Down Sequences The power supplies must be powered up in the following order: 1. VDD 2. VDDQ 3. VREF 4. Inputs The power-down sequence must be the reverse. VDDQ can be allowed to exceed VDD by no more than 0.6V. Application Example 2M x 18 SA LD R/W BW0 BW1 CC KK DQ0–17 ZQ SRAM #4 R=250 Ω Vt Data-In/Data-Out Address 0–65 LD R/W BW0–7 Memory Controller Return CLK Source CLK Return CLK Source CLK SA LD R/W BW0 BW1 CC KK DQ0–17 ZQ SRAM #1 R=250 Ω Vt R Vt Vt R=50 Ω Vt=VREF R 0–71 |
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