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IS42VS16100C1-10TI Datasheet(PDF) 8 Page - Integrated Silicon Solution, Inc |
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IS42VS16100C1-10TI Datasheet(HTML) 8 Page - Integrated Silicon Solution, Inc |
8 / 80 page IS42VS16100C1 ISSI® 8 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 04/15/05 OPERATING FREQUENCY / LATENCY RELATIONSHIPS SYMBOL PARAMETER -10 -10 UNITS — Clock Cycle Time 10 12 ns — Operating Frequency ( CAS Latency = 3) 100 83 MHz tCAC CAS Latency 3 2/3 cycle tRCD Active Command To Read/Write Command Delay Time 3 2 cycle tRAC RAS Latency (tRCD + tCAC) 6 4 cycle tRC Command Period (REF to REF / ACT to ACT) 10 8 cycle tRAS Command Period (ACT to PRE) 5 5 cycle tRP Command Period (PRE to ACT) 3 2 cycle tRRD Command Period (ACT[0] to ACT [1]) 2 2 cycle tCCD Column Command Delay Time 1 1 cycle (READ, READA, WRIT, WRITA) tDPL Input Data To Precharge Command Delay Time 2 2 cycle tDAL Input Data To Active/Refresh Command Delay Time 5 4 cycle (During Auto-Precharge) tRBD Burst Stop Command To Output in HIGH-Z Delay Time CAS Latency = 3 3 3 cycle (Read) CAS Latency = 2 — 2 tWBD Burst Stop Command To Input in Invalid Delay Time 0 0 cycle (Write) tRQL Precharge Command To Output in HIGH-Z Delay Time CAS Latency = 3 3 3 cycle (Read) CAS Latency = 2 — 2 tWDL Precharge Command To Input in Invalid Delay Time 0 0 cycle (Write) tPQL Last Output To Auto-Precharge Start Time (Read) CAS Latency = 3 -2 -2 cycle CAS Latency = 2 — -1 tQMD DQM To Output Delay Time (Read) 2 2 cycle tDMD DQM To Input Delay Time (Write) 0 0 cycle tMRD Mode Register Set To Command Delay Time 2 2 cycle AC TEST CONDITIONS (Input/Output Reference Level: 0.9V) I/O 50 Ω 0.5 x VDDQ V 30 pF Output Load Input tOH tAC 0.9V 0.9V tCH tCS tCK tCHI tCL 1.8V 0.9V 0.0V 1.8V 0.9V 0.0V CLK INPUT OUTPUT |
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