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IS43R16160A Datasheet(PDF) 1 Page - Integrated Silicon Solution, Inc |
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IS43R16160A Datasheet(HTML) 1 Page - Integrated Silicon Solution, Inc |
1 / 56 page Integrated Silicon Solution, Inc. — 1-800-379-4774 1 Rev. 00B 11/28/05 ISSI® IS43R16160A Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. FEATURES • Clock Frequency: 200, 166 MHz • Power supply (VDD and VDDQ) DDR 333: 2.5V + 0.2V DDR 400: 2.6V + 0.1V • SSTL 2 interface • Four internal banks to hide row Pre-charge and Active operations • Commands and addresses register on positive clock edges (CK) • Bi-directional Data Strobe signal for data cap- ture • Differential clock inputs (CK and CK) for two data accesses per clock cycle • Data Mask feature for Writes supported • DLL aligns data I/O and Data Strobe transitions with clock inputs • Half-strength and Full-strength drive strength options • Programmable burst length for Read and Write operations • Programmable CAS Latency (2, 2.5, or 3 clocks) • Programmable burst sequence: sequential or interleaved • Burst concatenation and truncation supported for maximum data throughput • Auto Pre-charge option for each Read or Write burst • 8192 refresh cycles every 64ms • Auto Refresh and Self Refresh Modes • Pre-charge Power Down and Active Power Down Modes • Lead-free available 16Meg x 16 256-MBIT DDR SDRAM PRELIMINARY INFORMATION NOVEMBER 2005 DEVICE OVERVIEW ISSI’s 256-Mbit DDR SDRAM achieves high-speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 268,435,456-bit memory array is internally organized as four banks of 64M-bit to allow concurrent operations. The pipeline allows Read and Write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. The programmable features of burst length, burst sequence and CAS latency enable further advantages. The device is available in 16-bit data word size. Input data is regis- tered on the I/O pins on both edges of Data Strobe signal(s), while output data is referenced to both edges of Data Strobe and both edges of CK. Commands are registered on the positive edges of CK. Auto Refresh, Active Power Down, and Pre-charge Power Down modes are enabled by using clock enable (CKE) and other inputs in an industry-standard sequence. All input and output voltage levels are compatible with SSTL 2. KEY TIMING PARAMETERS Parameter -5 -6 Unit DDR400 DDR333 Clock Cycle Time CAS Latency = 3 5 6 ns CAS Latency = 2.5 6 6 ns CAS Latency = 2 7.5 7.5 ns Clock Frequency CAS Latency = 3 200 166 MHz CAS Latency = 2.5 166 166 MHz CAS Latency = 2 133 133 MHz |
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