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IS42S16400C1-7TLI Datasheet(PDF) 1 Page - Integrated Silicon Solution, Inc |
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IS42S16400C1-7TLI Datasheet(HTML) 1 Page - Integrated Silicon Solution, Inc |
1 / 55 page Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1 Rev. E 10/25/05 IS42S16400C1 ISSI® Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. FEATURES • Clock frequency: 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single 3.3V power supply • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst sequence: Sequential/Interleave • Self refresh modes • 4096 refresh cycles every 64 ms • Random column address every clock cycle • Programmable CAS latency (2, 3 clocks) • Burst read/write and burst read/single write operations capability • Burst termination by burst stop and precharge command • Byte controlled by LDQM and UDQM • Industrial temperature availability • Package: 400-mil 54-pin TSOP II • Lead-free package is available OVERVIEW ISSI's 64Mb Synchronous DRAM IS42S16400C1 is organized as 1,048,576 bits x 16-bit x 4-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. 1 Meg Bits x 16 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM OCTOBER 2005 PIN CONFIGURATIONS 54-Pin TSOP (Type II) VDD DQ0 VDDQ DQ1 DQ2 GNDQ DQ3 DQ4 VDDQ DQ5 DQ6 GNDQ DQ7 VDD LDQM WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 GND DQ15 GNDQ DQ14 DQ13 VDDQ DQ12 DQ11 GNDQ DQ10 DQ9 VDDQ DQ8 GND NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 GND PIN DESCRIPTIONS A0-A11 Address Input BA0, BA1 Bank Select Address DQ0 to DQ15 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe Command CAS Column Address Strobe Command WE Write Enable LDQM Lower Bye, Input/Output Mask UDQM Upper Bye, Input/Output Mask VDD Power GND Ground VDDQ Power Supply for DQ Pin GNDQ Ground for DQ Pin NC No Connection |
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